116 Commits

Author	SHA1	Message	Date
Alex Forencich	fd908dd2aa	Clean up clock connections	2020-08-06 17:15:38 -07:00
Alex Forencich	f0e130aa48	Add AU50 10G example design	2020-07-17 00:06:32 -07:00
Alex Forencich	2570c75a0c	Clean up AU280 design	2020-07-16 23:55:12 -07:00
Alex Forencich	f2f3c0f977	Add AU280 10G example design	2020-07-15 00:06:38 -07:00
Alex Forencich	b7c089dd22	XDC clean up	2020-07-13 23:58:30 -07:00
Alex Forencich	3898cf21ed	Add DE2-115 example design	2020-07-10 15:38:43 -07:00
Alex Forencich	3b06f86dcf	Add C10LP example design	2020-07-10 15:32:39 -07:00
Alex Forencich	a27c04a949	Convert to TCL IP	2020-07-01 19:43:26 -07:00
Alex Forencich	73bd619d85	Add NetFPGA SUME example design	2020-03-27 19:01:50 -07:00
Alex Forencich	27ed447005	Use common sync_reset module files	2020-03-27 18:27:45 -07:00
Alex Forencich	a55c354924	Parametrize Ethernet frame parsing	2020-02-21 21:37:57 -08:00
Alex Forencich	4ac6d6803b	Parametrize ARP components	2020-02-20 16:49:47 -08:00
Alex Forencich	815705f413	Add VCU1525 10G example design	2020-01-15 23:14:08 -08:00
Alex Forencich	b34f294900	Add ExaNIC X25 10G example design	2019-10-30 17:14:27 -07:00
Alex Forencich	b3c654461e	Update example design	2019-10-22 23:17:39 -07:00
Alex Forencich	c5e886769a	Fix typo	2019-07-19 10:29:55 -07:00
Alex Forencich	16e5ec2106	Update example designs	2019-07-18 17:13:47 -07:00
Alex Forencich	e5171d8749	Enable flash programming in VCU118 example designs	2019-07-01 17:51:31 -07:00
Alex Forencich	386ff91210	Add ExaNIC X10 flash programming commands	2019-06-27 01:27:32 -07:00
Alex Forencich	d62a5ad050	Fix quotes	2019-06-27 01:26:58 -07:00
Alex Forencich	dfafa9c83d	Update vivado.mk	2019-06-27 00:59:36 -07:00
Alex Forencich	025f05e667	Add nojournal and nolog	2019-06-27 00:48:20 -07:00
Alex Forencich	af4f675840	Fix for dash	2019-06-27 00:15:36 -07:00
Alex Forencich	cfcd9da375	Update IP	2019-06-26 20:50:05 -07:00
Alex Forencich	15b3aaf2e7	Update programming commands	2019-06-26 20:17:45 -07:00
Alex Forencich	963a8f7459	Add flash ADM-PCIE-9V3 flash programming commands	2019-06-26 20:06:22 -07:00
Alex Forencich	88cc4e6e24	Update VCU108 flash programming commands	2019-06-26 19:50:28 -07:00
Alex Forencich	dc4416a261	Update Arty flash programming commands	2019-06-26 19:00:20 -07:00
Alex Forencich	d166350d77	Update Arty XDC	2019-06-26 18:59:41 -07:00
Alex Forencich	daf1d3106f	Enable flash programming on VCU108	2019-06-26 01:28:54 -07:00
Alex Forencich	7cce7896b5	Update programming commands	2019-06-25 23:46:44 -07:00
Alex Forencich	0927f4c326	Fix readme	2019-06-19 23:51:04 -07:00
Alex Forencich	1eb9c39ed3	Add VCU118 25G example design	2019-06-19 23:25:06 -07:00
Alex Forencich	1a28b0bf67	Add ADM-PCIE-9V3 25G example design	2019-06-19 23:22:56 -07:00
Alex Forencich	a031993b26	Update example designs	2019-06-19 23:16:57 -07:00
Alex Forencich	27999924a0	Update VCU108 example designs	2019-06-15 17:35:49 -07:00
Alex Forencich	352f52e159	Add flash target to Arty example design	2019-05-27 01:02:55 -07:00
Alex Forencich	249f9d9df4	Update example designs	2019-05-10 22:55:44 -07:00
Alex Forencich	2abb413854	Fix signal name	2019-05-02 20:30:37 -07:00
Alex Forencich	1d61626785	Add KC705 GMII example design	2019-05-02 19:29:47 -07:00
Alex Forencich	978fdce95c	Minor fixes	2019-04-03 20:57:10 -07:00
Alex Forencich	5428d81fd6	Update AXI stream switch instances	2019-03-28 23:56:06 -07:00
Alex Forencich	0008956828	Add Arty example design	2019-03-28 19:38:55 -07:00
Alex Forencich	0ca8c9a59b	Update example design timing constraints	2019-03-28 17:59:30 -07:00
Alex Forencich	e120a85607	Use correct clock	2019-03-28 17:56:55 -07:00
Alex Forencich	d16d291d5e	Upgrade example design IP cores	2019-03-28 16:30:34 -07:00
Alex Forencich	cd6b87e984	Enable bitstream compression in example designs	2019-02-06 21:25:30 -08:00
Alex Forencich	52058cb5de	Swap out PHY in VCU118 example design	2019-02-05 18:28:42 -08:00
Alex Forencich	5f6e7f721c	Update testbench	2019-01-31 18:12:07 -08:00
Alex Forencich	07b4efa9ba	Switch out Xilinx PHY core in ExaNIC X10 example design	2019-01-18 13:49:46 -08:00