FPGA/verilog-ethernet
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6 Commits

Author SHA1 Message Date
Alex Forencich
fd908dd2aa Clean up clock connections 2020-08-06 17:15:38 -07:00
Alex Forencich
a27c04a949 Convert to TCL IP 2020-07-01 19:43:26 -07:00
Alex Forencich
27ed447005 Use common sync_reset module files 2020-03-27 18:27:45 -07:00
Alex Forencich
a55c354924 Parametrize Ethernet frame parsing 2020-02-21 21:37:57 -08:00
Alex Forencich
16e5ec2106 Update example designs 2019-07-18 17:13:47 -07:00
Alex Forencich
1a28b0bf67 Add ADM-PCIE-9V3 25G example design 2019-06-19 23:22:56 -07:00