FPGA/verilog-ethernet
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3 Commits

Author SHA1 Message Date
Alex Forencich
d166350d77 Update Arty XDC 2019-06-26 18:59:41 -07:00
Alex Forencich
352f52e159 Add flash target to Arty example design 2019-05-27 01:02:55 -07:00
Alex Forencich
0008956828 Add Arty example design 2019-03-28 19:38:55 -07:00