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  • 53b3618c2a
         Merge 7761a95abe1a6948285cd3bb32f39bf31f8c12de into baac5f8d811d43853d59d69957975ead8bbed088 kvsh2050 2025-01-08 13:08:21 +05:30
  • 7761a95abe fully working - with bitstream kvsh2050 2025-01-08 11:38:54 +05:30
  • 36e34cf4e3 fully functional kvsh2050 2025-01-08 11:20:09 +05:30
  • 8f5fde54c1 fully functional - readme kvsh2050 2025-01-08 10:19:38 +05:30
  • 39186e155d fully functional - for artix kvsh2050 2025-01-08 10:17:38 +05:30
  • 0e2ea63a11 fully functional - for artix kvsh2050 2025-01-08 10:16:11 +05:30
  • ec84831ebf fully functional - for artix kvsh2050 2025-01-08 10:13:47 +05:30
  • ee63e79568 Allow manual test run Oliver Bunting 2025-01-03 15:18:13 +00:00
  • d6fa52a37d
         Update to compile (#1) ollie 2025-01-03 15:15:20 +00:00
  • 0cf111fad7
         Merge b502b3a4558b3692ceca619dbf212dc3cd7f8557 into baac5f8d811d43853d59d69957975ead8bbed088 Drew Ranck 2024-10-04 00:54:39 +00:00
  • b502b3a455
         Update axis_xgmii_tx_64.v Drew Ranck 2024-10-03 20:45:54 -04:00
  • 81454e705f
         Merge f762edd71dfebc129dacac64ff5cd5fbf7d67801 into baac5f8d811d43853d59d69957975ead8bbed088 Lucas Bollen 2024-07-18 10:54:44 +02:00
  • f762edd71d remove IODDR_STYLE from ssio_sdr_in instantiation in ssio_sdr_in_diff Lucas Bollen 2024-07-18 10:53:46 +02:00
  • 56d9686251
         Merge 6b3b024f14be3cf3dc0ef072b734235df5cddf07 into baac5f8d811d43853d59d69957975ead8bbed088 Jonathan Kimmitt 2024-03-08 15:09:02 +00:00
  • 6b3b024f14 Add VC707 board example Jonathan Kimmitt 2024-03-08 15:00:26 +00:00
  • 935d590812
         Merge e5c59803485f9f600d909bb2e41b7c782bd628a3 into baac5f8d811d43853d59d69957975ead8bbed088 renardo18 2024-02-23 11:04:38 -08:00
  • e5c5980348 Fixed a special case: When udp_checksum_gen_64 is outputing a long packet, and enough 1-word packets are entering into this module, the last one is written into FIFO but it's header is never being written into the header_mem because it's full Renaud Di Bernardo 2024-02-23 10:57:33 -08:00
  • 3491d9b22c
         Merge 089e030edfc7ec033c21bfc41d8e77212345999b into baac5f8d811d43853d59d69957975ead8bbed088 hannodewind 2024-02-19 02:24:40 -07:00
  • 71188b1a1e
         Merge 7e570709f2844396ac6e3cc48538c1141175e4a9 into baac5f8d811d43853d59d69957975ead8bbed088 Leon Schuermann 2024-02-19 02:24:40 -07:00
  • 2f7258f860
         Merge cef6b47bb3b969120cabce3b89b0c98bb47ca6a9 into baac5f8d811d43853d59d69957975ead8bbed088 Ilia Sergachev 2024-02-19 02:24:39 -07:00
  • 4399517033
         Merge 7df1cbd59610af60848525dc4425f793c75cf9c1 into baac5f8d811d43853d59d69957975ead8bbed088 jrrk 2024-02-19 02:24:39 -07:00
  • d06bca6b91
         Merge 8f038fc9daf8843b2f7f700983146e078aab4b00 into baac5f8d811d43853d59d69957975ead8bbed088 Christer Weinigel 2024-02-19 02:24:39 -07:00
  • 4bf7429107
         Merge b616e0760a7e0e654140ed5489dff1a122fc8e54 into baac5f8d811d43853d59d69957975ead8bbed088 Aaron Cleaver 2024-02-19 02:24:39 -07:00
  • 8d9ce11da7
         Merge 4da7d350b8f4d186d8e3a7ab369920827929eb3f into baac5f8d811d43853d59d69957975ead8bbed088 Anderson Ignacio 2024-02-19 02:24:39 -07:00
  • d12e144e13
         Merge de868fef18bfcadaee2fa6c1ef889a4fa22ca021 into baac5f8d811d43853d59d69957975ead8bbed088 david-sawatzke 2024-02-16 17:58:45 -05:00
  • 1ace211ad4
         Merge 3f12de79e3c13ea78a2676db693102d3f2ad10e9 into baac5f8d811d43853d59d69957975ead8bbed088 Víctor Mayoral Vilches 2024-02-16 17:58:10 -05:00
  • b11d824dd2
         Merge ae9d2e919bc53c4dfa68e0dcf75d0adddf1dbf71 into baac5f8d811d43853d59d69957975ead8bbed088 Víctor Mayoral Vilches 2024-02-15 11:55:47 +00:00
  • a21ac36cca
         Merge 0d9fcb11591e2aa579d30f0ceba25840124b8ec4 into baac5f8d811d43853d59d69957975ead8bbed088 mkravch 2024-02-15 11:55:47 +00:00
  • be9303fb8d
         Merge 31c1f3ccb5cde24e43d3677d6f4f2602e3954f28 into baac5f8d811d43853d59d69957975ead8bbed088 Briansune 2024-02-13 22:25:59 -08:00
  • 442f06a5ff
         Merge 9e6c137787834a850f2a3cc5c3efe2369f295958 into baac5f8d811d43853d59d69957975ead8bbed088 Viktor Prutyanov 2024-02-13 22:25:46 -08:00
  • baac5f8d81 Reorganize PTP timestamp capture logic; determine PTP clock step size from PTP time instead of parameters master Alex Forencich 2024-02-12 17:29:31 -08:00
  • 839fe8cbbe Add ptp_td_rel2tod module for timestamp reconstruction Alex Forencich 2024-02-11 13:01:29 -08:00
  • c5d069444a Move alternate offset switch near the end of the current second to extend reconstruction range for timestamps in the past Alex Forencich 2024-02-11 13:01:03 -08:00
  • 870cebb798 Clean up PTP parameters on MACs Alex Forencich 2024-02-11 13:00:37 -08:00
  • ae17f7db00 Remove extraneous scaleb(-9) in set_ts_tod_ns in ptp_td so that the seconds field can be set correctly Alex Forencich 2024-02-09 15:12:19 -08:00
  • 22abe6cacb merged changes in axis Alex Forencich 2024-02-05 17:30:40 -08:00
  • 0ac15c6872 Split out and pipeline relative timestamp LSB increment in PTP TD leaf clock Alex Forencich 2024-02-05 16:22:02 -08:00
  • eb0f01f276 Rework MAC TX error handling to streamline logic; pad errored frames to avoid generating runt frames Alex Forencich 2024-01-29 18:33:14 -08:00
  • e24f887009 Add TX underrun and error tests Alex Forencich 2024-01-29 16:16:11 -08:00
  • 915f4c21ff Cleanup RGMII PHY IF, fix TX error indication Alex Forencich 2024-01-29 16:10:58 -08:00
  • b784f23c71 Fix wait end state in GMII TX Alex Forencich 2024-01-28 21:31:55 -08:00
  • 13c1872a42 Clean up XGMII symbol generation Alex Forencich 2024-01-28 20:36:06 -08:00
  • 10b6d2f5bc Force AXIS RAM switch output FIFO into distributed RAM Alex Forencich 2024-01-28 16:38:38 -08:00
  • 0d3f5fbbc4 Handle framing errors in payload state in XGMII RX module Alex Forencich 2024-01-28 14:53:15 -08:00
  • 685df9317f Unconditionally transfer out XGMII data in XGMII RX modules Alex Forencich 2024-01-28 14:43:59 -08:00
  • 8074748564 Move timestamp capture into payload state in XGMII RX module Alex Forencich 2024-01-28 14:43:18 -08:00
  • f37bb1fc8d Rework termination character handling in XGMII RX modules Alex Forencich 2024-01-27 14:06:32 -08:00
  • c6ecd770e7 Fix spurious multi-driven net issue in axis_ram_switch when S_ID_WIDTH = 0 Alex Forencich 2024-01-26 12:35:27 -08:00
  • 12744433de merged changes in axis Alex Forencich 2024-01-17 15:10:47 -08:00
  • a29282cdda Remove stall cycle in axis_arb_mux Alex Forencich 2024-01-17 15:08:57 -08:00
  • e493c6cdb4 Fix FIFO output pause logic Alex Forencich 2024-01-17 12:17:11 -08:00
  • b4d09cbbdf More extensive overhaul of the PTP period output module to improve resource consumption and parallelize computation Alex Forencich 2024-01-16 17:01:03 -08:00
  • f313fafc70 Separate locked status from fast-forward mode in PTP period output module Alex Forencich 2024-01-15 22:55:50 -08:00
  • f400372b1c Add missing assign to frame_min_count_reg in axis_xgmii_tx_32 module Alex Forencich 2024-01-14 20:51:14 -08:00
  • b22db1d2d2 Add CRC state registers where possible to 10G/25G MAC modules Alex Forencich 2024-01-14 19:17:00 -08:00
  • f08eb74666 Optimize block type decoding in 10G PHY RX to reduce fanin Alex Forencich 2024-01-14 16:14:57 -08:00
  • 74936e83c5 Add register on PRBS checker output in 10G PHY RX to improve timing performance Alex Forencich 2024-01-14 16:10:20 -08:00
  • a05d1a4550 Rename Arista_7132LB to DCS7132LB Alex Forencich 2024-01-14 15:45:38 -08:00
  • 5ce57158ee Fix padding on 32-bit axis xgmii converter Víctor Jiménez Rugama 2023-12-19 18:31:51 +01:00
  • dce0c92a57 Rework PHC to register shared adder outputs for improved timing performance Alex Forencich 2023-12-02 00:53:02 -08:00
  • dd97924714 Prevent stale data frim being used to sync leaf clock Alex Forencich 2023-12-01 22:05:53 -08:00
  • f0c47db509 Improve tolerance of sample point synchronization Alex Forencich 2023-12-01 22:03:14 -08:00
  • a2294c56a5 Rewrite gain scheduling Alex Forencich 2023-12-01 22:02:40 -08:00
  • 89ee44d410 Add test for PCIe spread spectrum clocking Alex Forencich 2023-12-01 22:02:09 -08:00
  • 36cf9c9b06 Remove unnecessary shadow valid registers Alex Forencich 2023-12-01 14:03:55 -08:00
  • be0d9b7b88 Improve handling of instance name mangling Alex Forencich 2023-12-01 13:37:25 -08:00
  • 5560fa2b32 Fix timestamp capture/sync logic Alex Forencich 2023-11-30 14:05:16 -08:00
  • 16cd84123d Add user_sma_clk pins to VCU108 and VCU118 constraints files Alex Forencich 2023-11-29 13:58:22 -08:00
  • 7f9fed6f84 Update readme Alex Forencich 2023-11-10 16:56:42 -08:00
  • 3535e53746 Add example design for Alveo U55C and Alveo U55N/Varium C1100 Alex Forencich 2023-11-10 15:40:14 -08:00
  • fe5f6aa3f5 Merge AU50 into Alveo example design Alex Forencich 2023-11-10 15:32:38 -08:00
  • de818ad621 Merge AU280 into Alveo example design Alex Forencich 2023-11-10 15:30:37 -08:00
  • 58732ebeb3 Rework Alveo parametrization Alex Forencich 2023-11-10 15:25:38 -08:00
  • 0986d1e901 Rework 7132 parametrization Alex Forencich 2023-11-08 13:36:21 -08:00
  • 1b29a88b18 Rename AU200 to Alveo Alex Forencich 2023-11-08 11:50:50 -08:00
  • bd8e8e5b20 Add PTP time distribution components Alex Forencich 2023-11-07 13:07:15 -08:00
  • 009560f583 Use latest version of cocotbext-eth Alex Forencich 2023-11-07 12:18:46 -08:00
  • 01badce3a1 Remove unnecessary resets Alex Forencich 2023-11-01 18:30:32 -07:00
  • 0d9fcb1159 upd make script mkrav 2023-10-17 13:24:23 +03:00
  • 1855d30dd7 add ex design for kcu105 Michail 2023-10-15 11:36:20 +03:00
  • 49513b45d4 Merge AU200, AU250, and VCU1525 designs Alex Forencich 2023-10-12 22:51:07 -07:00
  • e84da8dbfb Update HTG-9200 readmes Alex Forencich 2023-09-26 23:12:52 -07:00
  • b5d1fadb7e Add makefiles for VU13P variant of HTG-9200 Alex Forencich 2023-09-26 15:07:16 -07:00
  • 5ff1e17a29 Add missing assign to frame_min_count_reg in axis_baser_tx_64 module Alex Forencich 2023-09-24 13:35:29 -07:00
  • 90e6dfc638 Use phase detector in PTP CDC module for coarse period tuning, use 9 LSBs of timestamp for fine sync to avoid rollover corrections, reduce FNS comparison width to 4 bits Alex Forencich 2023-09-23 14:58:44 -07:00
  • a9e3d3cae8 Wait longer to ensure PTP CDC module has fully stabilized in MAC testbenches Alex Forencich 2023-09-23 14:52:48 -07:00
  • f9ae6da8bd Improve PTP CDC module testbench Alex Forencich 2023-09-23 14:33:14 -07:00
  • 5a37442706 Merge FNS registers into NS registers in PTP CDC module Alex Forencich 2023-09-22 22:52:59 -07:00
  • b0a4d75fd9 Remove extraneous code Alex Forencich 2023-09-22 01:08:01 -07:00
  • 4a32c86f07 Match integrator width to period register width in PTP CDC module Alex Forencich 2023-09-22 01:07:43 -07:00
  • cf441f004d Rename source sync signals in PTP CDC module for consistency Alex Forencich 2023-09-22 01:07:12 -07:00
  • 4b1f48ab5b Parameter clean-up in PTP CDC module Alex Forencich 2023-09-21 16:34:05 -07:00
  • aad30d09a1 Make FNS_WIDTH an internal parameter in PTP CDC module Alex Forencich 2023-09-21 16:30:29 -07:00
  • fe720ebe47 frame_min_count was never updated, so padding was not working Renaud Di Bernardo 2023-09-21 08:54:29 -07:00
  • 98b4fbb56d Remove USE_SAMPLE_CLOCK parameter in PTP CDC module Alex Forencich 2023-09-18 16:58:02 -07:00
  • 060e55b915 Wait for correct PTP CDC instance to lock Alex Forencich 2023-09-18 16:39:30 -07:00
  • b316c6764e Use quad wrappers in ExaNIC X25 example design Alex Forencich 2023-08-26 12:44:50 -07:00
  • f9eda00d68 Use quad wrappers in ExaNIC X10 example design Alex Forencich 2023-08-26 12:43:29 -07:00
  • dc58b2447f Use quad wrappers in ZCU102 example design Alex Forencich 2023-08-26 12:42:39 -07:00
  • d5df47d8b0 Use quad wrappers in ZCU106 example design Alex Forencich 2023-08-26 12:42:04 -07:00