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  • 4618edcd8e Use quad wrappers in VCU108 example design Alex Forencich 2023-08-26 01:15:29 -07:00
  • 72de6c653a Use quad wrappers in AU50 example design Alex Forencich 2023-08-26 01:09:00 -07:00
  • 66987c8f62 Use quad wrappers in AU280 example design Alex Forencich 2023-08-26 01:08:32 -07:00
  • 22f327b35f Use quad wrappers in AU250 example design Alex Forencich 2023-08-26 01:07:30 -07:00
  • 65361d157b Use quad wrappers in AU200 example design Alex Forencich 2023-08-26 01:06:28 -07:00
  • bd06e57764 Use quad wrappers in VCU1525 example design Alex Forencich 2023-08-26 01:05:23 -07:00
  • c673ddbc14 Use quad wrappers in fb2CG@KU15P example design Alex Forencich 2023-08-26 00:37:44 -07:00
  • 5d61059488 Use quad wrappers in ADM-PCIE-9V3 example design Alex Forencich 2023-08-26 00:36:39 -07:00
  • 1e88ed3d2e Update readme Alex Forencich 2023-08-25 23:12:59 -07:00
  • 68736d02ae Add 10G/25G design for Arista 7132LB-48Y4C switch Alex Forencich 2023-08-25 23:06:49 -07:00
  • 351ec79fef Use quad wrappers in VCU118 example designs Alex Forencich 2023-08-25 01:27:53 -07:00
  • 75c2cc0acc Use quad wrappers in HTG9200 example designs Alex Forencich 2023-08-25 01:24:26 -07:00
  • aaeeb05ac0 Fix PHY configuration connections Alex Forencich 2023-08-25 00:09:38 -07:00
  • fa05d4ff3c Add TX and RX enable inputs to MACs Alex Forencich 2023-08-24 01:24:33 -07:00
  • 20c542051d Use cfg prefix for configuration signals Alex Forencich 2023-08-22 17:14:52 -07:00
  • f92a94d278 merged changes in axis Alex Forencich 2023-08-16 16:19:04 -07:00
  • 7823b916bf Implement MARK_WHEN_FULL option in FIFOs Alex Forencich 2023-08-16 12:50:12 -07:00
  • 6020d09214 Reorganize FIFO write logic Alex Forencich 2023-08-14 18:55:02 -07:00
  • c3cd676c5d Test DROP_WHEN_FULL parameter Alex Forencich 2023-08-14 16:59:57 -07:00
  • c4f298de6f Add overflow test, previous test is actually an oversize frame test Alex Forencich 2023-08-14 16:59:30 -07:00
  • 330d6f41fc Send more data in stress tests Alex Forencich 2023-08-14 16:59:14 -07:00
  • 3a665f0ded Compute DEPTH based on FIFO data width Alex Forencich 2023-08-14 16:58:35 -07:00
  • 7febd080c9 Use FIFO depth in overflow test Alex Forencich 2023-08-14 16:58:22 -07:00
  • ac2c0fdac8 Read configuration directly from DUT Alex Forencich 2023-08-14 16:57:30 -07:00
  • 62c2148c8f Add pause functionality to FIFO modules Alex Forencich 2023-08-14 16:57:16 -07:00
  • e308c9559a Rewrite width converter to reduce resource consumption Alex Forencich 2023-08-14 16:56:54 -07:00
  • 31bac4e21f Reorganize FIFO adapter wrappers Alex Forencich 2023-08-14 16:56:33 -07:00
  • d6fc68947b Procedural generation of testbench drivers Alex Forencich 2023-07-27 20:25:08 -07:00
  • 6b00ff29c8 merged changes in axis Alex Forencich 2023-07-27 01:45:14 -07:00
  • 1628a1a043 Reorganize pipeline FIFO to facilitate placement constraints Alex Forencich 2023-07-27 01:43:36 -07:00
  • 10da93fec4 Add depth status outputs to FIFOs Alex Forencich 2023-07-26 20:02:43 -07:00
  • 2be72bb758 Refactor pointer handling in FIFOs Alex Forencich 2023-07-26 18:47:43 -07:00
  • 9cb38fa2a0 Remove extraneous parameters Alex Forencich 2023-07-26 16:48:28 -07:00
  • a443e8862c Update TCL timing constraints to handle clocks from OOC IP that are not constrained during synthesis Alex Forencich 2023-07-26 14:59:19 -07:00
  • 4f7c0ebe2a merged changes in axis Alex Forencich 2023-07-26 14:53:57 -07:00
  • 9bc052de8b Another update to async FIFO timing constraints to deal with OOC clock constraints Alex Forencich 2023-07-26 14:53:01 -07:00
  • 02ce168c63 Improve PTP-related tests Alex Forencich 2023-07-24 01:01:54 -07:00
  • fa173f93e5 Avoid testbench reset during alignment test Alex Forencich 2023-07-24 00:57:43 -07:00
  • 70cc19ff15 Add MAC control layer to core 1G and 10G MAC modules Alex Forencich 2023-07-23 22:24:42 -07:00
  • 78284572ef Remove XDC constraints that do not apply to Artix 7 Alex Forencich 2023-07-23 18:35:22 -07:00
  • ba5a883433 Add pause/PFC modules Alex Forencich 2023-07-23 16:31:33 -07:00
  • 6d5cda5986 Add MAC control layer modules Alex Forencich 2023-07-22 00:47:15 -07:00
  • b1177eb4ed Rename HXT100G to HTG-640 Alex Forencich 2023-07-21 18:17:26 -07:00
  • 5d349c9cb2 Enable overtemp shutdown in constraints files Alex Forencich 2023-07-21 18:17:12 -07:00
  • f4a8561652 Add HTG-9200 + HTG 6x QSFP28 example design Alex Forencich 2023-07-21 18:16:59 -07:00
  • 6bf727d3ef Add VCU118 + HTG 6x QSFP28 example design Alex Forencich 2023-07-21 18:16:20 -07:00
  • 31901754a6 Add FMC pins to VCU118 Alex Forencich 2023-07-21 16:55:55 -07:00
  • 19a76cbaf9 Add FMC pins to VCU108 Alex Forencich 2023-07-21 16:55:44 -07:00
  • 72a35c08ef Clean up FMC+ pins on HTG-9200 Alex Forencich 2023-07-21 16:55:19 -07:00
  • bdc974a60c Reorganize HTG-9200 PLL config Alex Forencich 2023-07-21 16:34:11 -07:00
  • efb3747967 Add IO delay false paths to HTG-9200 constraints file Alex Forencich 2023-07-20 21:15:20 -07:00
  • 4a65e3594c Connect all PLL control lines on HTG-9200 board Alex Forencich 2023-07-20 01:17:49 -07:00
  • 375b12865f Use QSFP Si570 for both QSFP modules on VCU118 Alex Forencich 2023-07-19 17:00:33 -07:00
  • 1be196279f Fix FIFO instances in S10DX example design Alex Forencich 2023-07-17 11:05:24 -07:00
  • 2858aaaef7 Add TX PTP timestamp enable bit in tuser Alex Forencich 2023-07-17 10:58:40 -07:00
  • 50b6f53387 Update testbench clock frequencies Alex Forencich 2023-07-15 01:53:31 -07:00
  • d3fb11b2c3 Use unified 10G/25G design for HTG9200 Alex Forencich 2023-07-13 21:35:42 -07:00
  • 412df8fea0 Use unified 10G/25G design for fb2CG@KU15P Alex Forencich 2023-07-13 21:34:53 -07:00
  • 026a302c1c Use unified 10G/25G design for ExaNIC X25 Alex Forencich 2023-07-13 20:45:47 -07:00
  • 5dc38f11b7 Use unified 10G/25G design for Alveo VCU1525 Alex Forencich 2023-07-13 20:42:40 -07:00
  • a221adc468 Use unified 10G/25G design for Alveo U50 Alex Forencich 2023-07-13 20:40:38 -07:00
  • 147435dfe1 Use unified 10G/25G design for Alveo U280 Alex Forencich 2023-07-13 20:38:34 -07:00
  • ea80d853ed Use unified 10G/25G design for Alveo U250 Alex Forencich 2023-07-13 19:53:21 -07:00
  • 0b18633bb1 Use unified 10G/25G design for Alveo U200 Alex Forencich 2023-07-13 19:49:25 -07:00
  • 489ee73355 Use unified 10G/25G design for VCU118 Alex Forencich 2023-07-13 19:02:57 -07:00
  • 729c5a61ce Use unified 10G/25G design for ADM-PCIE-9V3 Alex Forencich 2023-07-13 18:59:33 -07:00
  • 48cbe43fa7 Update Vivado makefiles Alex Forencich 2023-07-13 18:48:34 -07:00
  • b6a9092a9f Update makefiles for Intel devices Alex Forencich 2023-07-13 17:46:34 -07:00
  • c4376c8674 Update XDC files Alex Forencich 2023-07-13 17:12:32 -07:00
  • 905e6c6358 Add PTP timestamping tests for 1G MAC Alex Forencich 2023-07-08 01:41:35 -07:00
  • 9665df8a44 Fix PTP timestamping in 1G MAC Alex Forencich 2023-07-08 01:41:14 -07:00
  • 1f0b6a625c PTP parameter clean-up Alex Forencich 2023-07-06 16:46:32 -07:00
  • 9dafc3aaee Use internal BYTE_LANES parameter Alex Forencich 2023-07-06 16:28:08 -07:00
  • 9159425cd8 Use correct payload lengths Alex Forencich 2023-06-29 22:18:50 -07:00
  • f705646e3e Pull out header size as a parameter Alex Forencich 2023-06-29 15:48:39 -07:00
  • ae9d2e919b Add KR260 fpga_10g_ddr reference design Víctor Mayoral Vilches 2023-05-02 13:41:58 +02:00
  • 271f5a08cc Add tcl for zynq_ps Víctor Mayoral Vilches 2023-04-11 16:25:34 +02:00
  • ada377c1c5 re-Add again Víctor Mayoral Vilches 2023-04-02 00:47:24 +02:00
  • 9212b89e93 Comment out additions, validate that starting point builds Víctor Mayoral Vilches 2023-04-02 00:17:37 +02:00
  • a34217d076 Add zynq_ps to KR260 10g example design Víctor Mayoral Vilches 2023-04-02 00:00:32 +02:00
  • 690d8555df Add devcontainer environment for the repo Víctor Mayoral Vilches 2023-02-27 17:57:52 +01:00
  • 325991277e Rename reference design to fpga_10g Víctor Mayoral Vilches 2023-03-11 09:10:55 +01:00
  • 3f12de79e3 Add devcontainer environment for the repo Víctor Mayoral Vilches 2023-02-27 17:57:52 +01:00
  • 2e69f50e30 Re-instantiate the same IP used in other TBs Víctor Mayoral Vilches 2023-03-10 14:33:39 +01:00
  • 7d3d1c81bc Update README, remove license needs, part of WEBPACK Víctor Mayoral Vilches 2023-03-10 14:23:46 +01:00
  • d1c11af089 Remove debounce_switch and clean up code Víctor Mayoral Vilches 2023-03-10 14:22:45 +01:00
  • ee97f7a454 Remove TB build results Víctor Mayoral Vilches 2023-03-10 14:18:50 +01:00
  • 8dcb5c888e Add KR260 reference design example Víctor Mayoral Vilches 2023-03-09 17:49:56 +01:00
  • c4c53f16c5
         Fix ber mon DavidMonk00 2023-03-03 09:45:37 +01:00
  • 12c8569dc0
         Merge 34f8067b9bbde723cee6796b32fcd8cc11d48296 into 77adf30dad1883e1603cf99fe036339a25b79007 Torsten Reuschel 2023-02-23 19:16:04 +08:00
  • 77adf30dad Add missing serdes_rx_reset_req output to 10G MAC+PHY modules Alex Forencich 2023-02-22 17:36:01 -08:00
  • 5f15cdeb24 Update ubuntu version in CI Alex Forencich 2023-02-17 16:05:02 -08:00
  • c65161e696 Remove recursively-expanded macros for module parameters in makefiles Alex Forencich 2023-02-17 16:04:16 -08:00
  • db818b2f53 merged changes in axis Alex Forencich 2023-02-17 16:03:28 -08:00
  • 960a2eab61 Remove recursively-expanded macros for module parameters in makefiles Alex Forencich 2023-02-17 15:56:40 -08:00
  • 5f1ad94041 Update ubuntu version in CI Alex Forencich 2023-02-13 13:03:06 -08:00
  • 9e6c137787 README: add Genesys2 (Xilinx Kintex 7 XC7K325T) Viktor Prutyanov 2023-02-08 00:05:27 +03:00
  • f0a606f287 example: Genesys2: fix README Viktor Prutyanov 2023-02-07 21:01:51 +03:00
  • 66dcb9cbf3 example: Genesys2: fix reset, remove UART RTS/CTS ports Viktor Prutyanov 2023-02-07 20:57:02 +03:00
  • e93a85df07 example: Genesys2: use proper XDC Viktor Prutyanov 2023-02-07 20:54:10 +03:00