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Commit Graph

  • 96a26e7a54 Add attributes to RAMs for proper synthesis in Quartus Alex Forencich 2021-11-02 20:22:47 -07:00
  • 6b18e56cb1 Add default_nettype none and resetall directives Alex Forencich 2021-10-20 17:29:12 -07:00
  • 9ff4454db0 Update makefiles Alex Forencich 2021-10-20 17:21:58 -07:00
  • 0f2478d68c Fix wires Alex Forencich 2021-10-20 17:21:16 -07:00
  • 1e6d667ae0 merged changes in axis Alex Forencich 2021-10-20 15:36:38 -07:00
  • 2972a1fa81 Add default_nettype none and resetall directives Alex Forencich 2021-10-20 15:33:38 -07:00
  • 786eabac4b Add missing wires Alex Forencich 2021-10-20 02:01:33 -07:00
  • 9f6f388a3c Rework GT instances in HTG9200 design Alex Forencich 2021-10-20 00:57:11 -07:00
  • 527c2f1b89 Rework GT instances in fb2CG@KU15P design Alex Forencich 2021-10-20 00:56:13 -07:00
  • 05770c5a1b Rework GT instances in VCU118 designs Alex Forencich 2021-10-19 22:13:02 -07:00
  • 531f751e67 Update VCU118 XDC Alex Forencich 2021-10-19 22:11:56 -07:00
  • cf016dc4ee Rework GT instances in VCU108 design Alex Forencich 2021-10-19 22:11:34 -07:00
  • 1f76eb4534 Update VCU108 XDC Alex Forencich 2021-10-19 22:10:32 -07:00
  • a1da0ba184 Rework GT instances in VCU1525 design Alex Forencich 2021-10-19 18:40:32 -07:00
  • 0b41dc4011 Rework GT instances in ZCU102 design Alex Forencich 2021-10-19 18:38:22 -07:00
  • e3f8879474 Rework GT instances in ZCU106 design Alex Forencich 2021-10-19 18:30:35 -07:00
  • 4ce218bc5d Rework GT instances in ADM-PCIE-9V3 designs Alex Forencich 2021-10-19 18:29:18 -07:00
  • 21da6f58dc Rework GT instances in Alveo U280 design Alex Forencich 2021-10-19 18:28:10 -07:00
  • 4fdc6408bc Rework GT instances in Alveo U50 design Alex Forencich 2021-10-19 18:14:50 -07:00
  • cc4256666a Rework GT instances in Alveo U250 design Alex Forencich 2021-10-19 17:47:15 -07:00
  • f11f7ecac9 Rework GT instances in Alveo U200 design Alex Forencich 2021-10-19 17:45:43 -07:00
  • 38e3244caa Rework GT instances in ExaNIC X10 design Alex Forencich 2021-10-18 00:34:06 -07:00
  • fa77fe54f3 Rework GT instances in ExaNIC X25 design Alex Forencich 2021-10-18 00:32:37 -07:00
  • 4aa672f8f3 Update example designs Alex Forencich 2021-10-17 20:20:26 -07:00
  • 625c48c59c Add transceiver reset watchdog Alex Forencich 2021-10-17 20:19:04 -07:00
  • 7594ac0775 Init and reset to same value Alex Forencich 2021-10-17 02:13:14 -07:00
  • 45ddd70036 merged changes in axis Alex Forencich 2021-10-17 01:42:17 -07:00
  • 2cd70281ea Properly zero synchronized pointer on one-sided reset Alex Forencich 2021-10-17 01:23:02 -07:00
  • 9d4d8508ae Unconditionally pass through ordered set data to simplify decode logic Alex Forencich 2021-10-16 01:25:48 -07:00
  • 247aeae845 Detect bad XGMII encodings in PHY TX Alex Forencich 2021-10-16 00:50:48 -07:00
  • 3b2e6874d8 Rework XGMII to BASE-R encoder implementation Alex Forencich 2021-10-16 00:48:01 -07:00
  • 9667ef1f9c Detect sequence errors Alex Forencich 2021-10-16 00:03:35 -07:00
  • 5258bdc312 Improve bad block detection Alex Forencich 2021-10-15 23:58:35 -07:00
  • 571394f99f Translate LPI control characters Alex Forencich 2021-10-15 23:53:53 -07:00
  • 5494f3b678 Rewrite resets Alex Forencich 2021-10-15 23:33:35 -07:00
  • a540e50e1c Fix XGMII to BASE-R control character mapping Alex Forencich 2021-10-15 16:14:02 -07:00
  • a539a76ec4 Add cocotb testbenches for 10G MAC+PHY modules Alex Forencich 2021-10-15 01:37:10 -07:00
  • e7dddc0dfd Add cocotb testbenches for AXI stream BASE-R TX and RX modules Alex Forencich 2021-10-15 01:08:14 -07:00
  • 8b95b33bab Add cocotb testbench for 10G PHY Alex Forencich 2021-10-15 01:07:26 -07:00
  • 2d9f01f9fe Add cocotb testbenches for XGMII BASE-R encoder and decoder modules Alex Forencich 2021-10-15 01:06:57 -07:00
  • c0e2eb2b07 Add BASE-R serdes models for cocotb Alex Forencich 2021-10-15 00:36:56 -07:00
  • 70cb88629b merged changes in axis Alex Forencich 2021-10-13 18:17:45 -07:00
  • 10e24cc5b1 Fix timing constraints Alex Forencich 2021-10-13 18:07:45 -07:00
  • 4c14289fb0 Fix instance name Alex Forencich 2021-10-13 14:43:42 -07:00
  • e85deafca3 Update FIFO instance Alex Forencich 2021-10-13 14:42:57 -07:00
  • 1d187b9b87 merged changes in axis Alex Forencich 2021-10-13 14:12:11 -07:00
  • 4f1eabab17 Split async FIFO resets Alex Forencich 2021-10-13 14:05:13 -07:00
  • 7e570709f2 Add Xilinx Kintex UltraScale+ KCU116 board Leon Schuermann 2021-10-08 12:30:08 +02:00
  • 4db6275f10 refactoring for clarity of local/nonlocal parameters and enforcing explicit declarations unbtorsten 2021-10-06 15:57:20 -03:00
  • e0da1819c4 More tests for pipeline FIFO Alex Forencich 2021-09-28 01:18:17 -07:00
  • 0b5fc5b0e0 Fix off by one error Alex Forencich 2021-09-28 01:17:57 -07:00
  • e48901a588 Reorganize test lists Alex Forencich 2021-09-28 01:17:28 -07:00
  • d549267e17 Test async FIFO with different clock periods Alex Forencich 2021-09-28 00:29:54 -07:00
  • a1e665c70f
         Update Makefile unbtorsten 2021-09-16 11:15:03 -03:00
  • 57b5bc9c4c
         add Genesys2 board to list of examples in README unbtorsten 2021-09-16 08:38:49 -03:00
  • 0d67fc616f adaptation for Genesys2 board, testbest has not been changed; implementation verified on hardware, but not by test bench unbtorsten 2021-09-16 08:37:07 -03:00
  • 670858e136 Merge branch 'Genesys2_board' derive example for Genesys2 board from Xilinx evaluation board KC705 which has the same FPGA unbtorsten 2021-09-16 08:28:02 -03:00
  • 839f9f7573 remove obsolete variants in Genesys2 board unbtorsten 2021-09-16 08:27:43 -03:00
  • 880c48d873 restore KC705 data unbtorsten 2021-09-16 08:26:58 -03:00
  • eb6b03487d derive Genesys2 board from Xilinx evaluation board KC705 which has the same FPGA unbtorsten 2021-09-16 08:26:31 -03:00
  • e8c28e00cd Update tox configuration Alex Forencich 2021-09-13 13:02:17 -07:00
  • c44e447db5 Transfer PTP information in tuser Alex Forencich 2021-09-01 15:56:00 -07:00
  • b6f792cc10 merged changes in axis Alex Forencich 2021-09-01 15:54:12 -07:00
  • 6c234260b2 Fix assignment type Alex Forencich 2021-09-01 15:53:15 -07:00
  • 3db970636c merged changes in axis Alex Forencich 2021-08-27 15:28:53 -07:00
  • 6bcd96fa83 Bypass pipeline FIFO when length is zero Alex Forencich 2021-08-27 13:54:14 -07:00
  • e7de9b6ee6 Update PTP CDC instances Alex Forencich 2021-08-26 01:07:56 -07:00
  • 77938fa422 Update MAC modules for changes in FIFO modules Alex Forencich 2021-08-26 00:55:12 -07:00
  • 5273a8dda6 merged changes in axis Alex Forencich 2021-08-26 00:14:22 -07:00
  • a613cc8a31 Fix alignment Alex Forencich 2021-08-25 23:58:52 -07:00
  • 6d70b0249e Update readme Alex Forencich 2021-08-25 23:58:33 -07:00
  • 6a030f5d5e Add axis_pipeline_fifo Alex Forencich 2021-08-25 23:54:30 -07:00
  • 92681fad8c Add DROP_OVERSIZE_FRAME parameter Alex Forencich 2021-08-25 22:56:22 -07:00
  • 0b2066abe3 Fix corner case with back-to-back single-cycle transfers Alex Forencich 2021-08-25 19:19:30 -07:00
  • ceeea4b451 modify acknowledge assign sungsoo.han 2021-08-17 16:42:26 +09:00
  • edaec3bd38 add LAST_ENABLE to axis_arb_mux sungsoo.han 2021-08-02 15:01:06 +09:00
  • 81673727a4 Fix broadcast address check Alex Forencich 2021-08-08 13:25:39 -07:00
  • 52d8867f73 Use BUFG instead of BUFIO2 for DDR input on Spartan 6 Alex Forencich 2021-07-31 12:45:38 -07:00
  • 3edbe52bfa Use BUFG instead of BUFIO2 for DDR input on Spartan 6 Alex Forencich 2021-07-31 12:43:33 -07:00
  • 90c4b0b409 bugs from distro? Mark Pesaresi 2021-07-29 22:50:50 +02:00
  • 29313d5e02 Add HTG-9200 10G example design Alex Forencich 2021-07-08 11:58:04 -07:00
  • cf832f581c Set algorithm for pytest-split Alex Forencich 2021-06-28 01:34:34 -07:00
  • 97182ccf4e Update vivado.mk Alex Forencich 2021-06-23 20:07:29 -07:00
  • 089e030edf udp_checksum_gen: fix issue where back-to-back header commits on a full header fifo causes a header to be dropped. Hanno de Wind 2021-06-18 08:28:20 +00:00
  • 201e0e7202 add test for header fifo overflow condition, currently failing for this issue Hanno de Wind 2021-06-18 08:13:36 +00:00
  • 763cc1669f Update test durations Alex Forencich 2021-06-03 13:52:41 -07:00
  • 5415c41c41 Remove string parameters Alex Forencich 2021-06-02 17:50:26 -07:00
  • 846183bc8b merged changes in axis Alex Forencich 2021-06-02 17:06:26 -07:00
  • 4fa3870dea Remove string parameters Alex Forencich 2021-06-02 15:08:43 -07:00
  • 0512664ae0 merged changes in axis Alex Forencich 2021-06-01 13:03:13 -07:00
  • 892ee84bff Delay command until write is acknowledged Alex Forencich 2021-05-31 01:32:02 -07:00
  • 3579310447 Clear active bit Alex Forencich 2021-05-31 01:31:30 -07:00
  • e32f65f563 Update test durations Alex Forencich 2021-05-30 12:39:49 -07:00
  • 5d9c982cd4 Add switch testbenches Alex Forencich 2021-05-30 12:33:29 -07:00
  • 34d5a4fed5 Add wrapper generator for RAM switch Alex Forencich 2021-05-30 12:32:26 -07:00
  • 9417d5f749 Use cocotb.top Alex Forencich 2021-05-30 12:32:02 -07:00
  • 16b174b490 Print addressing configuration Alex Forencich 2021-05-30 12:19:01 -07:00
  • e3183862bb tkeep always active inside RAM switch Alex Forencich 2021-05-30 12:12:10 -07:00
  • 56a3b8fe92 Fix indexed part select error in degenerate case when M_COUNT = 1 Alex Forencich 2021-05-30 12:11:46 -07:00
  • 8e5c4874eb Fix switch wrapper parameters Alex Forencich 2021-05-30 12:10:04 -07:00