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Commit Graph

  • c1bfa8cc41 Add tuser assert tests Alex Forencich 2021-05-25 00:55:59 -07:00
  • a7905ed681 Add stress tests Alex Forencich 2021-05-25 00:31:20 -07:00
  • a7ebfdcebb Add arbitration test Alex Forencich 2021-05-25 00:13:32 -07:00
  • b09e01ba48 Update S10MX SDC Alex Forencich 2021-05-19 21:57:48 -07:00
  • 9df253aa59 Update readme Alex Forencich 2021-05-19 21:57:33 -07:00
  • cee82cb695 Add Stratix 10 DX 10G example design Alex Forencich 2021-05-19 21:00:54 -07:00
  • 13c1bbe79a Update S10MX QSF Alex Forencich 2021-05-19 16:48:58 -07:00
  • 0c493c4ba1 Update readme Alex Forencich 2021-05-18 22:11:32 -07:00
  • 28686fb115 Update readme Alex Forencich 2021-05-18 22:05:44 -07:00
  • 20c7967715 Update readme Alex Forencich 2021-05-18 19:16:48 -07:00
  • bf6fddd1db Add Stratix 10 MX 10G example design Alex Forencich 2021-05-18 19:16:30 -07:00
  • 40265a3e1c Add timing constraints for Quartus Prime Pro Alex Forencich 2021-05-18 18:30:33 -07:00
  • 7751aba8da Reorganize timing constraints Alex Forencich 2021-05-18 16:15:41 -07:00
  • f236e7dff1 merged changes in axis Alex Forencich 2021-05-18 16:03:37 -07:00
  • b7f3faa628 Add timing constraints for Quartus Prime Pro Alex Forencich 2021-05-18 16:02:36 -07:00
  • e9f7723312 Reorganize timing constraints Alex Forencich 2021-05-16 23:28:00 -07:00
  • c77e82c0dd Add LAST_ENABLE parameter to axis-arb-mux Jeehoon Kang 2021-05-13 14:14:47 +09:00
  • 4da7d350b8
         Added STLV7325 board Anderson Ignacio da Silva 2021-05-07 17:35:49 +01:00
  • 5e1329a992 Rework PHY bitslip timing Alex Forencich 2021-05-05 00:35:43 -07:00
  • c021d01c26 Update example design readmes Alex Forencich 2021-05-04 15:48:12 -07:00
  • b616e0760a fix overflow in parameter sizes for ARP timeouts Aaron Cleaver 2021-04-15 15:37:04 +10:00
  • 244f136ca7 Remove travis-ci Alex Forencich 2021-04-03 17:09:12 -07:00
  • b56bc11598 Update readme Alex Forencich 2021-04-03 17:00:18 -07:00
  • 397a253584 Add Github Actions regression testing Alex Forencich 2021-04-03 16:57:14 -07:00
  • c884efc1f3 Add test durations for pytest-split Alex Forencich 2021-04-03 16:56:54 -07:00
  • 74c1014671 Add cocotb testbenches Alex Forencich 2021-04-03 16:53:08 -07:00
  • 17ba806687 Add tox and pytest configuration Alex Forencich 2021-04-03 16:36:46 -07:00
  • 9d99ec0096 Update wrapper generators Alex Forencich 2021-04-03 16:34:42 -07:00
  • 3df18fafdd Use nonblocking assignment Alex Forencich 2021-04-03 16:33:45 -07:00
  • 2796e681c9 Prevent latch inference Alex Forencich 2021-03-30 22:23:40 -07:00
  • 31c7349f90 Rewrite PTP clock CDC module for improved performance and timing closure at 25G Alex Forencich 2021-03-30 15:57:46 -07:00
  • 42950abf12 Refactor PTP period output, implement error output Alex Forencich 2021-03-30 15:25:34 -07:00
  • 00d69a341c Test with sample clock on and off Alex Forencich 2021-03-27 14:44:36 -07:00
  • 55359c1755 Report difference in ns Alex Forencich 2021-03-27 14:44:21 -07:00
  • 3cbe4b04da Improve timestamp difference measurement Alex Forencich 2021-03-27 14:38:35 -07:00
  • 1dd349399b PTP clock period is always positive Alex Forencich 2021-03-17 21:13:36 -07:00
  • a3f6e36777 Use release version of cocotb for CI Alex Forencich 2021-03-17 19:41:07 -07:00
  • 6f81c27045 Add readme for Atlys example design Alex Forencich 2021-03-16 13:52:01 -07:00
  • 2446001807 Add cocotb testbenche for arp Alex Forencich 2021-03-08 22:52:11 -08:00
  • f21f6296ac Add cocotb testbenches for arp_eth_rx and arp_eth_tx Alex Forencich 2021-03-08 22:51:27 -08:00
  • 20a56dc0d6 Refactor eth_axis_rx and eth_axis_tx testbenches Alex Forencich 2021-03-08 22:47:40 -08:00
  • 4af058fbdc Update testbenches Alex Forencich 2021-03-06 20:04:19 -08:00
  • 22b3bacf51 Update attribute name Alex Forencich 2021-03-05 23:03:41 -08:00
  • 730eaec733
         Merge 6abbe836fabc65686c1303bf947f5a49a9d82d3f into c0c2dbce2aeb7110031cb5d3020fbfe23c7609da Reisswolf 2021-02-17 23:24:29 +01:00
  • c0c2dbce2a Update XDC files Alex Forencich 2021-02-06 15:15:34 -08:00
  • eeb04acdd0 Update github actions Alex Forencich 2021-01-16 13:39:56 -08:00
  • 8f038fc9da Make examples/VC709 work Christer Weinigel 2021-01-03 23:18:48 +01:00
  • c148b1b367 Create examples/VC709 based on NetFPGA_SUME Christer Weinigel 2021-01-03 21:09:01 +01:00
  • a91e2b7e17 Add KC705 SGMII example design Alex Forencich 2020-12-30 17:15:34 -08:00
  • 5a7fd98413 Add KC705 RGMII example design Alex Forencich 2020-12-30 17:15:18 -08:00
  • 8a021f5c9b Update KC705 XDC Alex Forencich 2020-12-30 16:54:30 -08:00
  • 22feb53e1d Update example design readmes Alex Forencich 2020-12-30 16:48:37 -08:00
  • 8e1ad2eba6 Add cocotb testbench for ptp_clock_cdc Alex Forencich 2020-12-29 22:55:55 -08:00
  • 7117de682a Add cocotb testbench for ptp_perout Alex Forencich 2020-12-29 22:02:27 -08:00
  • 0171afbb18 Add cocotb testbench for ptp_clock Alex Forencich 2020-12-29 22:02:18 -08:00
  • e5bc5e1f49 Add cocotb testbench for arp_cache Alex Forencich 2020-12-29 22:01:24 -08:00
  • 25b890f8bb Remove extraneous code Alex Forencich 2020-12-29 18:55:13 -08:00
  • 77d22bfde0 Rework sim_build output directory, fix default makefile target Alex Forencich 2020-12-29 14:47:12 -08:00
  • 5a3d71823a Update readme Alex Forencich 2020-12-28 20:44:00 -08:00
  • 782d86a7d1 Remove readme link Alex Forencich 2020-12-28 20:43:26 -08:00
  • 731fd859ac Add Github Actions regression tests Alex Forencich 2020-12-28 20:19:58 -08:00
  • 4a98858bea Forward arguments to pytest Alex Forencich 2020-12-28 20:19:46 -08:00
  • f47c529122 Add test durations Alex Forencich 2020-12-28 19:33:56 -08:00
  • cd12721502 Add cococb testbenches for eth_axis_rx and eth_axis_tx Alex Forencich 2020-12-28 19:28:38 -08:00
  • 29dc7498d3 Add cocotb MAC testbenches Alex Forencich 2020-12-28 19:26:46 -08:00
  • 0359d8d76a Use absolute path to test directory Alex Forencich 2020-12-28 19:25:59 -08:00
  • a894af4815 Add tox.ini Alex Forencich 2020-12-28 01:12:08 -08:00
  • 079d6329cb Migrate example design testbenches to cocotb Alex Forencich 2020-12-28 01:11:03 -08:00
  • 4d31316fef Remove travis-ci Alex Forencich 2020-12-25 02:09:50 -08:00
  • d1fc821c8b Fix simulation startup issue in rgmii_phy_if Alex Forencich 2020-12-25 02:03:57 -08:00
  • a78627343d Change default target parameter Alex Forencich 2020-12-25 01:48:24 -08:00
  • 220e04d1a7 Update example design Alex Forencich 2020-12-25 01:47:01 -08:00
  • 2a2d8ac966 Fix reg type in VCU108 and VCU118 example designs Alex Forencich 2020-12-20 14:22:52 -08:00
  • d834e49587 Move wire declarations Alex Forencich 2020-12-03 17:37:53 -08:00
  • 1f9aa62639 Add wrapper generator for axis_broadcast Alex Forencich 2020-12-03 17:31:11 -08:00
  • 909ccae151 Properly synchronize bad FCS status output Alex Forencich 2020-12-01 14:01:15 -08:00
  • 306aa4db0b Update VCU118 XDC Alex Forencich 2020-10-06 00:39:32 -07:00
  • ed7136a095 Update flash programming configuration for ExaNIC X10 and X25 Alex Forencich 2020-10-03 15:27:30 -07:00
  • 9261f26f64 Update VCU108 XDC Alex Forencich 2020-10-02 20:50:00 -07:00
  • 9e4bd6e854 Fix flash programming commands for VCU108 Alex Forencich 2020-10-01 00:53:13 -07:00
  • 816e071a57 Fix bitstream config for VCU1525 Alex Forencich 2020-09-30 23:50:31 -07:00
  • bf9f1a6211 Update flash programming commands Alex Forencich 2020-09-29 18:29:27 -07:00
  • 3f52ed675c Fix flash settings Alex Forencich 2020-09-29 17:30:13 -07:00
  • 2bc052e0d5 Update LED driver timing constraints Alex Forencich 2020-09-28 17:24:11 -07:00
  • d0a45d8213 Add fb2CG flash programming commands Alex Forencich 2020-09-27 01:45:56 -07:00
  • 82cf0d5a6f Use correct init_clk frequency Alex Forencich 2020-09-23 14:24:18 -07:00
  • 99b06b0ed2 Update readme Alex Forencich 2020-09-22 23:04:44 -07:00
  • 6a4bcaab38 Add timing constraints for LED driver Alex Forencich 2020-09-22 22:13:59 -07:00
  • a7972e32bb Add fb2CG 10G example design Alex Forencich 2020-09-20 01:18:47 -07:00
  • c9d8b8508e Update readme Alex Forencich 2020-09-18 01:26:17 -07:00
  • 4db7f50ad8 Update readme Alex Forencich 2020-09-18 01:26:09 -07:00
  • c9a023c1e0 Add AU250 10G example design Alex Forencich 2020-09-18 01:20:42 -07:00
  • 6254158e1b Add AU200 10G example design Alex Forencich 2020-09-18 01:20:20 -07:00
  • b65bc94b4c Update readme Alex Forencich 2020-09-18 00:16:25 -07:00
  • 9a8ba2f0f2 Add ZCU102 example design Alex Forencich 2020-09-18 00:15:21 -07:00
  • 6df648ef54 merged changes in axis Alex Forencich 2020-09-07 18:55:12 -07:00
  • da152a8546 Update timing parameters for async FIFO to reflect new pipeline register naming Alex Forencich 2020-09-07 18:54:32 -07:00
  • 71b6b9f6f2 Prevent shift register inference Alex Forencich 2020-09-07 18:54:18 -07:00
  • dff38e2c1d Add UDP test script Alex Forencich 2020-09-07 16:32:00 -07:00
  • ad47169480 Add netns shell script Alex Forencich 2020-09-07 16:28:18 -07:00