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Commit Graph

  • 16e5ec2106 Update example designs Alex Forencich 2019-07-18 17:13:47 -07:00
  • 3bd7be44fa Update FIFO instances and update MACs to use combined FIFO adapter module Alex Forencich 2019-07-18 16:25:49 -07:00
  • 3a79b8fb17 merged changes in axis Alex Forencich 2019-07-18 11:50:56 -07:00
  • 8b2f37d5cc Update readme Alex Forencich 2019-07-18 11:28:19 -07:00
  • 69de6fd2a4 Convert FIFOs to use DEPTH parameter instead of ADDR_WIDTH Alex Forencich 2019-07-18 11:27:25 -07:00
  • e0a1a73ce0 Mask tdata with tkeep Alex Forencich 2019-07-18 11:01:00 -07:00
  • 4da1a83052 Constant FIFO depth Alex Forencich 2019-07-17 23:36:10 -07:00
  • 021c91fcc7 Unconditionally wait at least one delta cycle Alex Forencich 2019-07-16 00:37:20 -07:00
  • 583849e0db merged changes in axis Alex Forencich 2019-07-16 00:30:49 -07:00
  • 1d5a4db0d5 Unconditionally wait at least one delta cycle Alex Forencich 2019-07-16 00:30:19 -07:00
  • 1279dcbf47 Back out previous change Alex Forencich 2019-07-15 18:09:14 -07:00
  • cc1ff34f53 Add 64 bit timestamp support to ptp_clock_cdc Alex Forencich 2019-07-15 16:36:02 -07:00
  • 31cb54e67e Make old icarus verilog happy Alex Forencich 2019-07-15 16:15:50 -07:00
  • ef3a39e933 Update readme Alex Forencich 2019-07-15 15:31:25 -07:00
  • c719b57474 Update readme Alex Forencich 2019-07-15 15:27:46 -07:00
  • 9d553f2ad4 Also need to use tready Alex Forencich 2019-07-15 15:24:12 -07:00
  • d88ada105d Add PTP TS extract module Alex Forencich 2019-07-15 15:17:58 -07:00
  • 77bae7a77e Add PTP clock CDC module and testbench Alex Forencich 2019-07-15 15:16:17 -07:00
  • 31c1f3ccb5
         A complete Quartus Prime 17.1 project (Windows) Briansune 2019-07-05 17:17:16 +08:00
  • e5171d8749 Enable flash programming in VCU118 example designs Alex Forencich 2019-07-01 17:51:31 -07:00
  • fdfb517761 Add PTP perout module and testbench Alex Forencich 2019-06-27 01:30:18 -07:00
  • 386ff91210 Add ExaNIC X10 flash programming commands Alex Forencich 2019-06-27 01:27:32 -07:00
  • d62a5ad050 Fix quotes Alex Forencich 2019-06-27 01:26:58 -07:00
  • dfafa9c83d Update vivado.mk Alex Forencich 2019-06-27 00:59:36 -07:00
  • 025f05e667 Add nojournal and nolog Alex Forencich 2019-06-27 00:48:20 -07:00
  • af4f675840 Fix for dash Alex Forencich 2019-06-27 00:15:36 -07:00
  • cfcd9da375 Update IP Alex Forencich 2019-06-26 20:50:05 -07:00
  • 15b3aaf2e7 Update programming commands Alex Forencich 2019-06-26 20:17:45 -07:00
  • 963a8f7459 Add flash ADM-PCIE-9V3 flash programming commands Alex Forencich 2019-06-26 20:06:22 -07:00
  • 88cc4e6e24 Update VCU108 flash programming commands Alex Forencich 2019-06-26 19:50:28 -07:00
  • dc4416a261 Update Arty flash programming commands Alex Forencich 2019-06-26 19:00:20 -07:00
  • d166350d77 Update Arty XDC Alex Forencich 2019-06-26 18:59:41 -07:00
  • daf1d3106f Enable flash programming on VCU108 Alex Forencich 2019-06-26 01:28:54 -07:00
  • 7cce7896b5 Update programming commands Alex Forencich 2019-06-25 23:46:44 -07:00
  • df04d7e68d CRC handling logic optimizations Alex Forencich 2019-06-20 18:10:53 -07:00
  • 9e7f4a9836 Remove unused state bit Alex Forencich 2019-06-20 18:02:15 -07:00
  • 0927f4c326 Fix readme Alex Forencich 2019-06-19 23:51:04 -07:00
  • 4410d74848 Update readme Alex Forencich 2019-06-19 23:28:15 -07:00
  • 1eb9c39ed3 Add VCU118 25G example design Alex Forencich 2019-06-19 23:25:06 -07:00
  • 1a28b0bf67 Add ADM-PCIE-9V3 25G example design Alex Forencich 2019-06-19 23:22:56 -07:00
  • a031993b26 Update example designs Alex Forencich 2019-06-19 23:16:57 -07:00
  • eb1f38a749 More critical path optimizations Alex Forencich 2019-06-19 15:06:55 -07:00
  • 134ce04777 Add configurable serdes pipeline register chain Alex Forencich 2019-06-19 00:57:28 -07:00
  • 3ba91ce091 Wait for block lock Alex Forencich 2019-06-19 00:53:41 -07:00
  • 303dec8165 Sum errors across data and header Alex Forencich 2019-06-19 00:25:41 -07:00
  • 1d3554c37e Rework pointer handling to improve timing Alex Forencich 2019-06-16 23:53:26 -07:00
  • 7ec836baf6 IP header checksum optimizations Alex Forencich 2019-06-16 22:01:11 -07:00
  • b17966f73d store_last_word timing optimization Alex Forencich 2019-06-16 20:01:08 -07:00
  • 55bf44117b shift_axis_extra_cycle timing optimization Alex Forencich 2019-06-16 19:57:52 -07:00
  • 3b959b2765 CRC handling logic optimizations Alex Forencich 2019-06-16 17:39:28 -07:00
  • 320a45c4ab Remove unused state bit Alex Forencich 2019-06-16 17:33:14 -07:00
  • 8bb243cd35 MAC termination detect timing optimizations Alex Forencich 2019-06-16 15:44:41 -07:00
  • 4f97303e44 Remove unused code Alex Forencich 2019-06-16 15:38:35 -07:00
  • 938479c246 MAC RX timing optimizations Alex Forencich 2019-06-16 00:36:50 -07:00
  • 27999924a0 Update VCU108 example designs Alex Forencich 2019-06-15 17:35:49 -07:00
  • 3684ccafb2 Make use of blocking statements consistent Alex Forencich 2019-06-15 16:56:45 -07:00
  • b2cacc4e94 Update readme Alex Forencich 2019-06-14 00:26:07 -07:00
  • d96a5a449a Update ARP cache testbench Alex Forencich 2019-06-14 00:01:51 -07:00
  • ce13522085 Implement ARP cache clear Alex Forencich 2019-06-14 00:01:13 -07:00
  • b41ab00381 Initialize ARP cache Alex Forencich 2019-06-13 23:45:17 -07:00
  • 296744b37e Make use of blocking statements consistent Alex Forencich 2019-06-12 23:31:03 -07:00
  • 7ccd520d2c merged changes in axis Alex Forencich 2019-06-10 17:45:02 -07:00
  • ced2df141c Add false path for async FIFO implementation in distributed RAM Alex Forencich 2019-06-10 17:40:30 -07:00
  • 75d9154d32 Reduce extraneous warnings from get_cells Alex Forencich 2019-06-10 17:39:18 -07:00
  • 6eff2f0030 Decouple transmit PTP tag enable and transmit PTP timestamp enable Alex Forencich 2019-06-09 22:03:24 -07:00
  • 20bb430ae9 merged changes in axis Alex Forencich 2019-06-09 18:59:03 -07:00
  • ccc15324a6 Fix bad frame mask Alex Forencich 2019-06-09 18:46:49 -07:00
  • 2794c315e8 Fix synthesizer complaints Alex Forencich 2019-06-08 17:36:09 -07:00
  • 82fe5a6bdd Add PTP timestamp capture logic to MACs Alex Forencich 2019-06-07 16:38:36 -07:00
  • 659aa67481 Pack start packet strobes into the same signal Alex Forencich 2019-06-06 17:13:14 -07:00
  • 2efcfdb0a0 Add PTP clock simulation model Alex Forencich 2019-06-03 19:08:16 -07:00
  • e181ea5abc Add PTP clock module and testbench Alex Forencich 2019-06-03 19:00:28 -07:00
  • 352f52e159 Add flash target to Arty example design Alex Forencich 2019-05-27 01:02:55 -07:00
  • 3da3725429 Disable bit slipping when RX PRBS check is enabled Alex Forencich 2019-05-16 23:22:47 -07:00
  • 249f9d9df4 Update example designs Alex Forencich 2019-05-10 22:55:44 -07:00
  • 79ec137243 Add PRBS31 generation and checking to 10G PHY Alex Forencich 2019-05-10 20:28:45 -07:00
  • e34c72da1f Add missing parameter Alex Forencich 2019-05-10 17:23:55 -07:00
  • b7d297850c Move 10G PHY interface logic into separate modules Alex Forencich 2019-05-10 14:56:18 -07:00
  • 2abb413854 Fix signal name Alex Forencich 2019-05-02 20:30:37 -07:00
  • 1d61626785 Add KC705 GMII example design Alex Forencich 2019-05-02 19:29:47 -07:00
  • 8e969aa14c Add FIFO/width adapter wrapper modules Alex Forencich 2019-04-26 18:38:25 -07:00
  • e3fcb0fa1d Test shorter frames Alex Forencich 2019-04-26 18:36:09 -07:00
  • 696c634726 Add rx_bad_block outputs Alex Forencich 2019-04-17 00:16:45 -07:00
  • 18d6aab16d Update readme Alex Forencich 2019-04-03 22:32:06 -07:00
  • 978fdce95c Minor fixes Alex Forencich 2019-04-03 20:57:10 -07:00
  • 1bec485766 Fix constants Alex Forencich 2019-04-03 11:48:09 -07:00
  • 5428d81fd6 Update AXI stream switch instances Alex Forencich 2019-03-28 23:56:06 -07:00
  • 9d21bf0f7c merged changes in axis Alex Forencich 2019-03-28 23:51:06 -07:00
  • a9c7946368 Change parameter concatenation to increments of DEST_WIDTH Alex Forencich 2019-03-28 23:49:04 -07:00
  • 0008956828 Add Arty example design Alex Forencich 2019-03-28 19:38:55 -07:00
  • 8e2d936884 Add MII PHY interface, MAC wrappers, and testbenches Alex Forencich 2019-03-28 19:18:03 -07:00
  • 0ca8c9a59b Update example design timing constraints Alex Forencich 2019-03-28 17:59:30 -07:00
  • e120a85607 Use correct clock Alex Forencich 2019-03-28 17:56:55 -07:00
  • 58201866f3 Add timing constraints Alex Forencich 2019-03-28 17:53:51 -07:00
  • efab3d87a3 merged changes in axis Alex Forencich 2019-03-28 16:35:19 -07:00
  • ad3905ac4d Account for more merged registers Alex Forencich 2019-03-28 16:33:01 -07:00
  • d16d291d5e Upgrade example design IP cores Alex Forencich 2019-03-28 16:30:34 -07:00
  • 8285f94eaa Rename tx_sync regs Alex Forencich 2019-03-28 16:27:33 -07:00
  • 3eaed305f5 Connect TX underflow status outputs Alex Forencich 2019-03-28 16:27:15 -07:00
  • edcfd0dc40 Prevent SRL inference in synchronizers Alex Forencich 2019-03-28 12:36:32 -07:00