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Commit Graph

  • e89097c8b1 merged changes in axis Alex Forencich 2018-10-25 16:07:04 -07:00
  • be51f2b472 Update FIFO instantiations Alex Forencich 2018-10-25 16:06:32 -07:00
  • ded363b471 Rename status outputs Alex Forencich 2018-10-25 15:36:34 -07:00
  • ebe9d17bd5 Update readme Alex Forencich 2018-10-25 14:30:42 -07:00
  • ed4a2d73c2 Add axis_pipeline_register module Alex Forencich 2018-10-25 14:29:35 -07:00
  • ceedd0f8f5 Update readme Alex Forencich 2018-10-25 14:27:24 -07:00
  • 312d90addb Add wrapper generators Alex Forencich 2018-10-25 14:23:00 -07:00
  • 49d415d59f Disable dump file output under travis-ci Alex Forencich 2018-10-25 12:14:12 -07:00
  • e9d9f32150 Rename ports Alex Forencich 2018-10-25 12:00:34 -07:00
  • 6f4ab8f180 Rename ports Alex Forencich 2018-10-25 11:59:13 -07:00
  • 84a758f100 Rename ports Alex Forencich 2018-10-25 11:56:52 -07:00
  • 6c1ea89a66 Rename ports Alex Forencich 2018-10-25 11:52:08 -07:00
  • fd28040c40 Rename ports Alex Forencich 2018-10-25 11:30:35 -07:00
  • 7997a4a844 Rename ports Alex Forencich 2018-10-25 11:19:28 -07:00
  • 8d9da455cd Minor optimizations Alex Forencich 2018-10-25 10:29:31 -07:00
  • e926daabaf Update readme Alex Forencich 2018-10-25 10:24:42 -07:00
  • cb9f2132a4 Update parameter ordering Alex Forencich 2018-10-25 10:20:17 -07:00
  • 09a8fa51b6 Rename ports Alex Forencich 2018-10-25 10:19:32 -07:00
  • c47f3ea03d Update FIFO instance, rename ports Alex Forencich 2018-10-25 10:17:58 -07:00
  • d1ed1528b5 Update FIFO instance, rename ports Alex Forencich 2018-10-25 10:15:16 -07:00
  • 11d9dbe24a Merge axis_async_fifo and axis_async_frame_fifo, rename ports Alex Forencich 2018-10-25 09:53:38 -07:00
  • 36d0a8786f Merge axis_fifo and axis_frame_fifo, rename ports Alex Forencich 2018-10-24 23:16:06 -07:00
  • 3d2efef93a Update readme Alex Forencich 2018-10-24 22:25:02 -07:00
  • 2bb9f11c9e Use logical operators Alex Forencich 2018-10-24 22:24:27 -07:00
  • 3bbf8524d6 Compute DEST_WIDTH Alex Forencich 2018-10-24 22:21:31 -07:00
  • 9d813226d0 Convert generated demux to verilog parametrized demux Alex Forencich 2018-10-24 22:16:05 -07:00
  • 145ea2c40c Connect arbiter parameters to top level Alex Forencich 2018-10-24 21:09:00 -07:00
  • 2bf15706cd Convert generated mux to verilog parametrized mux Alex Forencich 2018-10-24 18:23:14 -07:00
  • 029d1fa06f Fix loop count variable scoping issue Alex Forencich 2018-10-24 17:58:39 -07:00
  • fc6c07e5f9 Convert generated frame joiner to verilog parametrized frame joiner Alex Forencich 2018-10-24 17:07:22 -07:00
  • fd7f65d5ad Convert generated switch to verilog parametrized switch Alex Forencich 2018-10-24 16:12:56 -07:00
  • 631147069f Rename ports and add reg_type parameter to axis_register Alex Forencich 2018-10-24 14:35:08 -07:00
  • 940c1210c1 Convert arbitrated mux to verilog parametrized arbitrated mux Alex Forencich 2018-10-24 13:49:17 -07:00
  • fe77db822d Convert generated crosspoint to verilog parametrized crosspoint Alex Forencich 2018-10-24 13:44:39 -07:00
  • 2c5679ff6a Update readme Alex Forencich 2018-10-24 10:59:02 -07:00
  • 4c711b8c7a Update readme Alex Forencich 2018-10-24 01:19:26 -07:00
  • fe0bf3b7c6 Remove old modules Alex Forencich 2018-10-24 01:08:27 -07:00
  • 00dc50826d Update example designs Alex Forencich 2018-10-24 01:03:44 -07:00
  • 0aca4c7dcc Update 10G MAC to use new modules Alex Forencich 2018-10-24 00:54:41 -07:00
  • de69975872 Add AXI stream XGMII RX and TX modules and testbenches Alex Forencich 2018-10-23 23:34:43 -07:00
  • 030fe90bf5 Fix example design testbench Alex Forencich 2018-10-19 15:33:25 -07:00
  • fbe698ebb7 Update Ethernet MAC testbenches Alex Forencich 2018-10-19 15:31:47 -07:00
  • 5e12f97518 MAC optimizations Alex Forencich 2018-10-19 15:24:33 -07:00
  • 553547f661 Fix test naming Alex Forencich 2018-09-09 13:52:13 -07:00
  • becfbf4425 When pausing the AXI stream model, do not drop tvalid if it is asserted and waiting for tready to be asserted Alex Forencich 2018-08-15 00:11:39 -07:00
  • 14d8819cd3 merged changes in axis Alex Forencich 2018-08-09 18:41:34 -07:00
  • 8e5ec36ced Optimize axis_arb_mux and improve latency Alex Forencich 2018-08-09 18:40:50 -07:00
  • 7a879aec1c Remove extra registers Alex Forencich 2018-08-09 18:38:41 -07:00
  • b5ec1c4a30 merged changes in axis Alex Forencich 2018-08-09 11:24:21 -07:00
  • 202fbcbb6f Fix typo Alex Forencich 2018-08-09 11:23:27 -07:00
  • 2e9602b5b4 Update testbenches to use wait Alex Forencich 2018-07-02 18:20:07 -07:00
  • 65c64588a6 More endpoint updates Alex Forencich 2018-07-02 16:33:13 -07:00
  • 7775e7774d merged changes in axis Alex Forencich 2018-07-02 16:26:21 -07:00
  • ffc63e4b0d Update readme Alex Forencich 2018-07-02 16:25:29 -07:00
  • 3063bba54b Update testbenches to use wait Alex Forencich 2018-07-02 16:19:35 -07:00
  • 9390c3639b More endpoint updates Alex Forencich 2018-07-02 14:13:47 -07:00
  • 63f9bbeced Update endpoints Alex Forencich 2018-07-02 13:20:49 -07:00
  • 4cb51ac84e merged changes in axis Alex Forencich 2018-07-02 10:25:51 -07:00
  • 268d011b89 Add wait method to sink Alex Forencich 2018-06-30 00:21:26 -07:00
  • 2ebffeb223 Be more pythonic Alex Forencich 2018-06-30 00:21:02 -07:00
  • 8982b4f4e1 Fix modsell pin Alex Forencich 2018-06-29 13:00:41 -07:00
  • cd51821bf7 Add parameters Alex Forencich 2018-06-22 18:56:05 -07:00
  • 5b7646ccda Rework ARP subsystem Alex Forencich 2018-06-18 13:59:58 -07:00
  • 25d1b373cc Use don't care bits Alex Forencich 2018-06-14 15:20:20 -07:00
  • 6368529b6f Add clock frequency annotation Alex Forencich 2018-06-14 13:42:10 -07:00
  • e4672915e6 Update testbenches to use instances() Alex Forencich 2018-06-13 22:43:11 -07:00
  • 20486d438a merged changes in axis Alex Forencich 2018-06-13 22:36:26 -07:00
  • c5837daa2f Update testbenches to use instances() Alex Forencich 2018-06-13 22:26:10 -07:00
  • 298ae4defa Update MAC module instantiation Alex Forencich 2018-06-13 22:16:02 -07:00
  • 8e1f14e9a7 Add VCU118 10G example design Alex Forencich 2018-06-13 19:30:07 -07:00
  • 05c6743473 Update xdc Alex Forencich 2018-06-13 19:18:59 -07:00
  • f4d7edf23f Add VCU118 example design Alex Forencich 2018-06-13 14:33:07 -07:00
  • 415f723edc Fix clock name Alex Forencich 2018-06-11 16:37:34 -07:00
  • fea477db09 Add unused ports Alex Forencich 2018-06-11 16:36:44 -07:00
  • 3ae97c71a0 Add documentation Alex Forencich 2018-06-04 18:21:55 -07:00
  • e95b39b36d Update iddr/oddr Altera device support Alex Forencich 2018-06-04 18:20:31 -07:00
  • c31757552b Add crosspoint design Alex Forencich 2018-05-31 16:27:56 -07:00
  • 855b593ce5 Minor updates to 10G example designs Alex Forencich 2018-05-31 16:05:41 -07:00
  • 3e28af152a Fix CI Alex Forencich 2018-02-27 11:00:31 -08:00
  • 6727e5a0bd Happy new year Alex Forencich 2018-02-27 01:47:56 -08:00
  • d0ef5f94a4 merge changes in axis Alex Forencich 2018-02-27 01:46:35 -08:00
  • 7c6da337b0 Happy new year Alex Forencich 2018-02-27 01:39:25 -08:00
  • 0fd157964a Happy new year Alex Forencich 2018-02-26 12:50:51 -08:00
  • 0807a54c32 merged changes in axis Alex Forencich 2018-02-26 12:45:29 -08:00
  • 5df7efe516 Happy new year Alex Forencich 2018-02-26 12:25:20 -08:00
  • 3063a761e5 Support both versions of ML605 Alex Forencich 2018-02-26 00:18:14 -08:00
  • bd27156f35 AXI stream updates Alex Forencich 2018-02-26 00:08:08 -08:00
  • 18787c2eed merged changes in axis Alex Forencich 2017-12-01 00:02:34 -08:00
  • c33985d7ba Remove extraneous parameter Alex Forencich 2017-11-21 08:54:21 -08:00
  • 93688dc88e Update readme Alex Forencich 2017-11-21 00:21:15 -08:00
  • 4ec4c901e8 Whitespace fixes Alex Forencich 2017-11-21 00:18:09 -08:00
  • b00eaf4d3c Add tkeep signal and update testbench for stat counter Alex Forencich 2017-11-21 00:17:42 -08:00
  • ad0e3e1eb5 Whitespace fixes and testbench update for frame joiner Alex Forencich 2017-11-21 00:16:15 -08:00
  • a1a6d523e3 Update FIFO instances and testbenches for COBS encoder and decoder Alex Forencich 2017-11-21 00:14:26 -08:00
  • 0edafd58ac Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream tap Alex Forencich 2017-11-20 23:45:34 -08:00
  • 4ef4ef2622 Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream SRL register Alex Forencich 2017-11-20 21:34:25 -08:00
  • b0d7820f5b Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream SRL FIFO Alex Forencich 2017-11-20 21:32:46 -08:00
  • d16f19f67e Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream rate limiter Alex Forencich 2017-11-20 21:31:41 -08:00
  • 772e433ee9 Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream frame length adjuster Alex Forencich 2017-11-20 21:30:26 -08:00
  • de590517a9 Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream switch Alex Forencich 2017-11-20 20:17:20 -08:00