#!/usr/bin/env python """ Copyright (c) 2020 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. """ import itertools import logging import os import cocotb_test.simulator import cocotb from cocotb.clock import Clock from cocotb.triggers import RisingEdge from cocotb.utils import get_time_from_sim_steps from cocotb.regression import TestFactory from cocotbext.eth import GmiiSink, PtpClockSimTime from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamFrame from cocotbext.axi.stream import define_stream PtpTsBus, PtpTsTransaction, PtpTsSource, PtpTsSink, PtpTsMonitor = define_stream("PtpTs", signals=["ts", "ts_valid"], optional_signals=["ts_tag", "ts_ready"] ) class TB: def __init__(self, dut): self.dut = dut self.log = logging.getLogger("cocotb.tb") self.log.setLevel(logging.DEBUG) self._enable_generator = None self._enable_cr = None cocotb.start_soon(Clock(dut.clk, 8, units="ns").start()) self.source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "s_axis"), dut.clk, dut.rst) self.sink = GmiiSink(dut.gmii_txd, dut.gmii_tx_er, dut.gmii_tx_en, dut.clk, dut.rst, dut.clk_enable, dut.mii_select) self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.clk) self.ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "m_axis_ptp"), dut.clk, dut.rst) dut.clk_enable.setimmediatevalue(1) dut.mii_select.setimmediatevalue(0) dut.cfg_ifg.setimmediatevalue(0) dut.cfg_tx_enable.setimmediatevalue(0) async def reset(self): self.dut.rst.setimmediatevalue(0) await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) self.dut.rst.value = 1 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) self.dut.rst.value = 0 await RisingEdge(self.dut.clk) await RisingEdge(self.dut.clk) def set_enable_generator(self, generator=None): if self._enable_cr is not None: self._enable_cr.kill() self._enable_cr = None self._enable_generator = generator if self._enable_generator is not None: self._enable_cr = cocotb.start_soon(self._run_enable()) def clear_enable_generator(self): self.set_enable_generator(None) async def _run_enable(self): for val in self._enable_generator: self.dut.clk_enable.value = val await RisingEdge(self.dut.clk) async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_gen=None, mii_sel=False): tb = TB(dut) tb.dut.cfg_ifg.value = ifg tb.dut.cfg_tx_enable.value = 1 tb.dut.mii_select.value = mii_sel if enable_gen is not None: tb.set_enable_generator(enable_gen()) await tb.reset() test_frames = [payload_data(x) for x in payload_lengths()] for test_data in test_frames: await tb.source.send(AxiStreamFrame(test_data, tuser=2)) for test_data in test_frames: rx_frame = await tb.sink.recv() ptp_ts = await tb.ptp_ts_sink.recv() ptp_ts_ns = int(ptp_ts.ts) / 2**16 rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns") tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns) tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns) tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns)) assert rx_frame.get_payload() == test_data assert rx_frame.check_fcs() assert rx_frame.error is None assert abs(rx_frame_sfd_ns - ptp_ts_ns - (32 if enable_gen else 8)) < 0.01 assert tb.sink.empty() await RisingEdge(dut.clk) await RisingEdge(dut.clk) def size_list(): return list(range(60, 128)) + [512, 1514] + [60]*10 def incrementing_payload(length): return bytearray(itertools.islice(itertools.cycle(range(256)), length)) def cycle_en(): return itertools.cycle([0, 0, 0, 1]) if cocotb.SIM_NAME: factory = TestFactory(run_test) factory.add_option("payload_lengths", [size_list]) factory.add_option("payload_data", [incrementing_payload]) factory.add_option("ifg", [12]) factory.add_option("enable_gen", [None, cycle_en]) factory.add_option("mii_sel", [False, True]) factory.generate_tests() # cocotb-test tests_dir = os.path.abspath(os.path.dirname(__file__)) rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) def test_axis_gmii_tx(request): dut = "axis_gmii_tx" module = os.path.splitext(os.path.basename(__file__))[0] toplevel = dut verilog_sources = [ os.path.join(rtl_dir, f"{dut}.v"), os.path.join(rtl_dir, "lfsr.v"), ] parameters = {} parameters['DATA_WIDTH'] = 8 parameters['ENABLE_PADDING'] = 1 parameters['MIN_FRAME_LENGTH'] = 64 parameters['PTP_TS_ENABLE'] = 1 parameters['PTP_TS_WIDTH'] = 96 parameters['PTP_TS_CTRL_IN_TUSER'] = parameters['PTP_TS_ENABLE'] parameters['PTP_TAG_ENABLE'] = parameters['PTP_TS_ENABLE'] parameters['PTP_TAG_WIDTH'] = 16 parameters['USER_WIDTH'] = ((parameters['PTP_TAG_WIDTH'] if parameters['PTP_TAG_ENABLE'] else 0) + (1 if parameters['PTP_TS_CTRL_IN_TUSER'] else 0) if parameters['PTP_TS_ENABLE'] else 0) + 1 extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} sim_build = os.path.join(tests_dir, "sim_build", request.node.name.replace('[', '-').replace(']', '')) cocotb_test.simulator.run( python_search=[tests_dir], verilog_sources=verilog_sources, toplevel=toplevel, module=module, parameters=parameters, sim_build=sim_build, extra_env=extra_env, )