FPGA/verilog-ethernet
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verilog-ethernet/example/520N_MX/fpga_10g/rtl
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Alex Forencich fa05d4ff3c Add TX and RX enable inputs to MACs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-08-24 01:24:33 -07:00
..
eth_xcvr_phy_quad_wrapper.v
Add 520N-MX 10G example design
2021-11-03 00:48:06 -07:00
eth_xcvr_phy_wrapper.v
Add 520N-MX 10G example design
2021-11-03 00:48:06 -07:00
fpga_core.v
Add TX and RX enable inputs to MACs
2023-08-24 01:24:33 -07:00
fpga.v
Add 520N-MX 10G example design
2021-11-03 00:48:06 -07:00
sync_signal.v
Add 520N-MX 10G example design
2021-11-03 00:48:06 -07:00