mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
603 lines
19 KiB
Verilog
603 lines
19 KiB
Verilog
/*
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga (
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/*
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* Clock: 300 MHz
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*/
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input wire usr_refclk0,
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/*
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* GPIO
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*/
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output wire [1:0] led_user_grn,
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output wire [1:0] led_user_red,
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output wire [3:0] led_qsfp,
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/*
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* Ethernet: QSFP28
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*/
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output wire [3:0] qsfp0_tx,
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input wire [3:0] qsfp0_rx,
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input wire qsfp0_refclk,
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output wire [3:0] qsfp1_tx,
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input wire [3:0] qsfp1_rx,
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input wire qsfp1_refclk,
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output wire [3:0] qsfp2_tx,
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input wire [3:0] qsfp2_rx,
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input wire qsfp2_refclk,
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output wire [3:0] qsfp3_tx,
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input wire [3:0] qsfp3_rx,
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input wire qsfp3_refclk,
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input wire [3:0] qsfp_irq_n
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);
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// Clock and reset
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wire ninit_done;
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reset_release reset_release_inst (
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.ninit_done (ninit_done)
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);
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wire clk_300mhz = usr_refclk0;
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wire rst_300mhz;
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sync_reset #(
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.N(4)
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)
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sync_reset_300mhz_inst (
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.clk(clk_300mhz),
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.rst(ninit_done),
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.out(rst_300mhz)
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);
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wire clk_156mhz_int;
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wire rst_156mhz_int;
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// XGMII 10G PHY
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// QSFP0
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wire qsfp0_tx_clk_1_int;
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wire qsfp0_tx_rst_1_int;
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wire [63:0] qsfp0_txd_1_int;
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wire [7:0] qsfp0_txc_1_int;
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wire qsfp0_rx_clk_1_int;
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wire qsfp0_rx_rst_1_int;
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wire [63:0] qsfp0_rxd_1_int;
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wire [7:0] qsfp0_rxc_1_int;
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wire qsfp0_tx_clk_2_int;
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wire qsfp0_tx_rst_2_int;
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wire [63:0] qsfp0_txd_2_int;
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wire [7:0] qsfp0_txc_2_int;
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wire qsfp0_rx_clk_2_int;
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wire qsfp0_rx_rst_2_int;
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wire [63:0] qsfp0_rxd_2_int;
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wire [7:0] qsfp0_rxc_2_int;
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wire qsfp0_tx_clk_3_int;
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wire qsfp0_tx_rst_3_int;
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wire [63:0] qsfp0_txd_3_int;
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wire [7:0] qsfp0_txc_3_int;
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wire qsfp0_rx_clk_3_int;
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wire qsfp0_rx_rst_3_int;
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wire [63:0] qsfp0_rxd_3_int;
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wire [7:0] qsfp0_rxc_3_int;
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wire qsfp0_tx_clk_4_int;
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wire qsfp0_tx_rst_4_int;
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wire [63:0] qsfp0_txd_4_int;
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wire [7:0] qsfp0_txc_4_int;
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wire qsfp0_rx_clk_4_int;
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wire qsfp0_rx_rst_4_int;
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wire [63:0] qsfp0_rxd_4_int;
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wire [7:0] qsfp0_rxc_4_int;
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assign clk_156mhz_int = qsfp0_tx_clk_1_int;
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assign rst_156mhz_int = qsfp0_tx_rst_1_int;
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wire qsfp0_rx_block_lock_1;
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wire qsfp0_rx_block_lock_2;
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wire qsfp0_rx_block_lock_3;
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wire qsfp0_rx_block_lock_4;
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eth_xcvr_phy_quad_wrapper qsfp0_eth_xcvr_phy_quad (
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.xcvr_ctrl_clk(clk_300mhz),
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.xcvr_ctrl_rst(rst_300mhz),
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.xcvr_ref_clk(qsfp0_refclk),
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.xcvr_tx_serial_data(qsfp0_tx),
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.xcvr_rx_serial_data(qsfp0_rx),
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.phy_1_tx_clk(qsfp0_tx_clk_1_int),
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.phy_1_tx_rst(qsfp0_tx_rst_1_int),
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.phy_1_xgmii_txd(qsfp0_txd_1_int),
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.phy_1_xgmii_txc(qsfp0_txc_1_int),
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.phy_1_rx_clk(qsfp0_rx_clk_1_int),
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.phy_1_rx_rst(qsfp0_rx_rst_1_int),
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.phy_1_xgmii_rxd(qsfp0_rxd_1_int),
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.phy_1_xgmii_rxc(qsfp0_rxc_1_int),
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.phy_1_rx_block_lock(qsfp0_rx_block_lock_1),
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.phy_1_rx_high_ber(),
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.phy_2_tx_clk(qsfp0_tx_clk_2_int),
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.phy_2_tx_rst(qsfp0_tx_rst_2_int),
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.phy_2_xgmii_txd(qsfp0_txd_2_int),
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.phy_2_xgmii_txc(qsfp0_txc_2_int),
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.phy_2_rx_clk(qsfp0_rx_clk_2_int),
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.phy_2_rx_rst(qsfp0_rx_rst_2_int),
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.phy_2_xgmii_rxd(qsfp0_rxd_2_int),
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.phy_2_xgmii_rxc(qsfp0_rxc_2_int),
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.phy_2_rx_block_lock(qsfp0_rx_block_lock_2),
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.phy_2_rx_high_ber(),
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.phy_3_tx_clk(qsfp0_tx_clk_3_int),
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.phy_3_tx_rst(qsfp0_tx_rst_3_int),
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.phy_3_xgmii_txd(qsfp0_txd_3_int),
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.phy_3_xgmii_txc(qsfp0_txc_3_int),
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.phy_3_rx_clk(qsfp0_rx_clk_3_int),
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.phy_3_rx_rst(qsfp0_rx_rst_3_int),
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.phy_3_xgmii_rxd(qsfp0_rxd_3_int),
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.phy_3_xgmii_rxc(qsfp0_rxc_3_int),
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.phy_3_rx_block_lock(qsfp0_rx_block_lock_3),
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.phy_3_rx_high_ber(),
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.phy_4_tx_clk(qsfp0_tx_clk_4_int),
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.phy_4_tx_rst(qsfp0_tx_rst_4_int),
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.phy_4_xgmii_txd(qsfp0_txd_4_int),
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.phy_4_xgmii_txc(qsfp0_txc_4_int),
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.phy_4_rx_clk(qsfp0_rx_clk_4_int),
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.phy_4_rx_rst(qsfp0_rx_rst_4_int),
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.phy_4_xgmii_rxd(qsfp0_rxd_4_int),
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.phy_4_xgmii_rxc(qsfp0_rxc_4_int),
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.phy_4_rx_block_lock(qsfp0_rx_block_lock_4),
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.phy_4_rx_high_ber()
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);
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// QSFP1
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wire qsfp1_tx_clk_1_int;
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wire qsfp1_tx_rst_1_int;
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wire [63:0] qsfp1_txd_1_int;
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wire [7:0] qsfp1_txc_1_int;
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wire qsfp1_rx_clk_1_int;
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wire qsfp1_rx_rst_1_int;
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wire [63:0] qsfp1_rxd_1_int;
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wire [7:0] qsfp1_rxc_1_int;
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wire qsfp1_tx_clk_2_int;
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wire qsfp1_tx_rst_2_int;
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wire [63:0] qsfp1_txd_2_int;
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wire [7:0] qsfp1_txc_2_int;
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wire qsfp1_rx_clk_2_int;
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wire qsfp1_rx_rst_2_int;
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wire [63:0] qsfp1_rxd_2_int;
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wire [7:0] qsfp1_rxc_2_int;
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wire qsfp1_tx_clk_3_int;
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wire qsfp1_tx_rst_3_int;
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wire [63:0] qsfp1_txd_3_int;
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wire [7:0] qsfp1_txc_3_int;
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wire qsfp1_rx_clk_3_int;
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wire qsfp1_rx_rst_3_int;
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wire [63:0] qsfp1_rxd_3_int;
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wire [7:0] qsfp1_rxc_3_int;
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wire qsfp1_tx_clk_4_int;
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wire qsfp1_tx_rst_4_int;
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wire [63:0] qsfp1_txd_4_int;
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wire [7:0] qsfp1_txc_4_int;
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wire qsfp1_rx_clk_4_int;
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wire qsfp1_rx_rst_4_int;
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wire [63:0] qsfp1_rxd_4_int;
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wire [7:0] qsfp1_rxc_4_int;
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wire qsfp1_rx_block_lock_1;
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wire qsfp1_rx_block_lock_2;
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wire qsfp1_rx_block_lock_3;
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wire qsfp1_rx_block_lock_4;
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eth_xcvr_phy_quad_wrapper qsfp1_eth_xcvr_phy_quad (
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.xcvr_ctrl_clk(clk_300mhz),
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.xcvr_ctrl_rst(rst_300mhz),
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.xcvr_ref_clk(qsfp1_refclk),
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.xcvr_tx_serial_data(qsfp1_tx),
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.xcvr_rx_serial_data(qsfp1_rx),
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.phy_1_tx_clk(qsfp1_tx_clk_1_int),
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.phy_1_tx_rst(qsfp1_tx_rst_1_int),
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.phy_1_xgmii_txd(qsfp1_txd_1_int),
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.phy_1_xgmii_txc(qsfp1_txc_1_int),
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.phy_1_rx_clk(qsfp1_rx_clk_1_int),
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.phy_1_rx_rst(qsfp1_rx_rst_1_int),
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.phy_1_xgmii_rxd(qsfp1_rxd_1_int),
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.phy_1_xgmii_rxc(qsfp1_rxc_1_int),
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.phy_1_rx_block_lock(qsfp1_rx_block_lock_1),
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.phy_1_rx_high_ber(),
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.phy_2_tx_clk(qsfp1_tx_clk_2_int),
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.phy_2_tx_rst(qsfp1_tx_rst_2_int),
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.phy_2_xgmii_txd(qsfp1_txd_2_int),
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.phy_2_xgmii_txc(qsfp1_txc_2_int),
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.phy_2_rx_clk(qsfp1_rx_clk_2_int),
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.phy_2_rx_rst(qsfp1_rx_rst_2_int),
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.phy_2_xgmii_rxd(qsfp1_rxd_2_int),
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.phy_2_xgmii_rxc(qsfp1_rxc_2_int),
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.phy_2_rx_block_lock(qsfp1_rx_block_lock_2),
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.phy_2_rx_high_ber(),
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.phy_3_tx_clk(qsfp1_tx_clk_3_int),
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.phy_3_tx_rst(qsfp1_tx_rst_3_int),
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.phy_3_xgmii_txd(qsfp1_txd_3_int),
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.phy_3_xgmii_txc(qsfp1_txc_3_int),
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.phy_3_rx_clk(qsfp1_rx_clk_3_int),
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.phy_3_rx_rst(qsfp1_rx_rst_3_int),
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.phy_3_xgmii_rxd(qsfp1_rxd_3_int),
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.phy_3_xgmii_rxc(qsfp1_rxc_3_int),
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.phy_3_rx_block_lock(qsfp1_rx_block_lock_3),
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.phy_3_rx_high_ber(),
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.phy_4_tx_clk(qsfp1_tx_clk_4_int),
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.phy_4_tx_rst(qsfp1_tx_rst_4_int),
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.phy_4_xgmii_txd(qsfp1_txd_4_int),
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.phy_4_xgmii_txc(qsfp1_txc_4_int),
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.phy_4_rx_clk(qsfp1_rx_clk_4_int),
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.phy_4_rx_rst(qsfp1_rx_rst_4_int),
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.phy_4_xgmii_rxd(qsfp1_rxd_4_int),
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.phy_4_xgmii_rxc(qsfp1_rxc_4_int),
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.phy_4_rx_block_lock(qsfp1_rx_block_lock_4),
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.phy_4_rx_high_ber()
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);
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// QSFP2
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wire qsfp2_tx_clk_1_int;
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wire qsfp2_tx_rst_1_int;
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wire [63:0] qsfp2_txd_1_int;
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wire [7:0] qsfp2_txc_1_int;
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wire qsfp2_rx_clk_1_int;
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wire qsfp2_rx_rst_1_int;
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wire [63:0] qsfp2_rxd_1_int;
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wire [7:0] qsfp2_rxc_1_int;
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wire qsfp2_tx_clk_2_int;
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wire qsfp2_tx_rst_2_int;
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wire [63:0] qsfp2_txd_2_int;
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wire [7:0] qsfp2_txc_2_int;
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wire qsfp2_rx_clk_2_int;
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wire qsfp2_rx_rst_2_int;
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wire [63:0] qsfp2_rxd_2_int;
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wire [7:0] qsfp2_rxc_2_int;
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wire qsfp2_tx_clk_3_int;
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wire qsfp2_tx_rst_3_int;
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wire [63:0] qsfp2_txd_3_int;
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wire [7:0] qsfp2_txc_3_int;
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wire qsfp2_rx_clk_3_int;
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wire qsfp2_rx_rst_3_int;
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wire [63:0] qsfp2_rxd_3_int;
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wire [7:0] qsfp2_rxc_3_int;
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wire qsfp2_tx_clk_4_int;
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wire qsfp2_tx_rst_4_int;
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wire [63:0] qsfp2_txd_4_int;
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wire [7:0] qsfp2_txc_4_int;
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wire qsfp2_rx_clk_4_int;
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wire qsfp2_rx_rst_4_int;
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wire [63:0] qsfp2_rxd_4_int;
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wire [7:0] qsfp2_rxc_4_int;
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wire qsfp2_rx_block_lock_1;
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wire qsfp2_rx_block_lock_2;
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wire qsfp2_rx_block_lock_3;
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wire qsfp2_rx_block_lock_4;
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eth_xcvr_phy_quad_wrapper qsfp2_eth_xcvr_phy_quad (
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.xcvr_ctrl_clk(clk_300mhz),
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.xcvr_ctrl_rst(rst_300mhz),
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.xcvr_ref_clk(qsfp2_refclk),
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.xcvr_tx_serial_data(qsfp2_tx),
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.xcvr_rx_serial_data(qsfp2_rx),
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.phy_1_tx_clk(qsfp2_tx_clk_1_int),
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.phy_1_tx_rst(qsfp2_tx_rst_1_int),
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.phy_1_xgmii_txd(qsfp2_txd_1_int),
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.phy_1_xgmii_txc(qsfp2_txc_1_int),
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.phy_1_rx_clk(qsfp2_rx_clk_1_int),
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.phy_1_rx_rst(qsfp2_rx_rst_1_int),
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.phy_1_xgmii_rxd(qsfp2_rxd_1_int),
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.phy_1_xgmii_rxc(qsfp2_rxc_1_int),
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.phy_1_rx_block_lock(qsfp2_rx_block_lock_1),
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.phy_1_rx_high_ber(),
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.phy_2_tx_clk(qsfp2_tx_clk_2_int),
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.phy_2_tx_rst(qsfp2_tx_rst_2_int),
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.phy_2_xgmii_txd(qsfp2_txd_2_int),
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.phy_2_xgmii_txc(qsfp2_txc_2_int),
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.phy_2_rx_clk(qsfp2_rx_clk_2_int),
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.phy_2_rx_rst(qsfp2_rx_rst_2_int),
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.phy_2_xgmii_rxd(qsfp2_rxd_2_int),
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.phy_2_xgmii_rxc(qsfp2_rxc_2_int),
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.phy_2_rx_block_lock(qsfp2_rx_block_lock_2),
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.phy_2_rx_high_ber(),
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.phy_3_tx_clk(qsfp2_tx_clk_3_int),
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.phy_3_tx_rst(qsfp2_tx_rst_3_int),
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.phy_3_xgmii_txd(qsfp2_txd_3_int),
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.phy_3_xgmii_txc(qsfp2_txc_3_int),
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.phy_3_rx_clk(qsfp2_rx_clk_3_int),
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.phy_3_rx_rst(qsfp2_rx_rst_3_int),
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.phy_3_xgmii_rxd(qsfp2_rxd_3_int),
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.phy_3_xgmii_rxc(qsfp2_rxc_3_int),
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.phy_3_rx_block_lock(qsfp2_rx_block_lock_3),
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.phy_3_rx_high_ber(),
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.phy_4_tx_clk(qsfp2_tx_clk_4_int),
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.phy_4_tx_rst(qsfp2_tx_rst_4_int),
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.phy_4_xgmii_txd(qsfp2_txd_4_int),
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.phy_4_xgmii_txc(qsfp2_txc_4_int),
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.phy_4_rx_clk(qsfp2_rx_clk_4_int),
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.phy_4_rx_rst(qsfp2_rx_rst_4_int),
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.phy_4_xgmii_rxd(qsfp2_rxd_4_int),
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.phy_4_xgmii_rxc(qsfp2_rxc_4_int),
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.phy_4_rx_block_lock(qsfp2_rx_block_lock_4),
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.phy_4_rx_high_ber()
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);
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|
|
|
// QSFP3
|
|
wire qsfp3_tx_clk_1_int;
|
|
wire qsfp3_tx_rst_1_int;
|
|
wire [63:0] qsfp3_txd_1_int;
|
|
wire [7:0] qsfp3_txc_1_int;
|
|
wire qsfp3_rx_clk_1_int;
|
|
wire qsfp3_rx_rst_1_int;
|
|
wire [63:0] qsfp3_rxd_1_int;
|
|
wire [7:0] qsfp3_rxc_1_int;
|
|
wire qsfp3_tx_clk_2_int;
|
|
wire qsfp3_tx_rst_2_int;
|
|
wire [63:0] qsfp3_txd_2_int;
|
|
wire [7:0] qsfp3_txc_2_int;
|
|
wire qsfp3_rx_clk_2_int;
|
|
wire qsfp3_rx_rst_2_int;
|
|
wire [63:0] qsfp3_rxd_2_int;
|
|
wire [7:0] qsfp3_rxc_2_int;
|
|
wire qsfp3_tx_clk_3_int;
|
|
wire qsfp3_tx_rst_3_int;
|
|
wire [63:0] qsfp3_txd_3_int;
|
|
wire [7:0] qsfp3_txc_3_int;
|
|
wire qsfp3_rx_clk_3_int;
|
|
wire qsfp3_rx_rst_3_int;
|
|
wire [63:0] qsfp3_rxd_3_int;
|
|
wire [7:0] qsfp3_rxc_3_int;
|
|
wire qsfp3_tx_clk_4_int;
|
|
wire qsfp3_tx_rst_4_int;
|
|
wire [63:0] qsfp3_txd_4_int;
|
|
wire [7:0] qsfp3_txc_4_int;
|
|
wire qsfp3_rx_clk_4_int;
|
|
wire qsfp3_rx_rst_4_int;
|
|
wire [63:0] qsfp3_rxd_4_int;
|
|
wire [7:0] qsfp3_rxc_4_int;
|
|
|
|
wire qsfp3_rx_block_lock_1;
|
|
wire qsfp3_rx_block_lock_2;
|
|
wire qsfp3_rx_block_lock_3;
|
|
wire qsfp3_rx_block_lock_4;
|
|
|
|
eth_xcvr_phy_quad_wrapper qsfp3_eth_xcvr_phy_quad (
|
|
.xcvr_ctrl_clk(clk_300mhz),
|
|
.xcvr_ctrl_rst(rst_300mhz),
|
|
.xcvr_ref_clk(qsfp3_refclk),
|
|
.xcvr_tx_serial_data(qsfp3_tx),
|
|
.xcvr_rx_serial_data(qsfp3_rx),
|
|
|
|
.phy_1_tx_clk(qsfp3_tx_clk_1_int),
|
|
.phy_1_tx_rst(qsfp3_tx_rst_1_int),
|
|
.phy_1_xgmii_txd(qsfp3_txd_1_int),
|
|
.phy_1_xgmii_txc(qsfp3_txc_1_int),
|
|
.phy_1_rx_clk(qsfp3_rx_clk_1_int),
|
|
.phy_1_rx_rst(qsfp3_rx_rst_1_int),
|
|
.phy_1_xgmii_rxd(qsfp3_rxd_1_int),
|
|
.phy_1_xgmii_rxc(qsfp3_rxc_1_int),
|
|
.phy_1_rx_block_lock(qsfp3_rx_block_lock_1),
|
|
.phy_1_rx_high_ber(),
|
|
.phy_2_tx_clk(qsfp3_tx_clk_2_int),
|
|
.phy_2_tx_rst(qsfp3_tx_rst_2_int),
|
|
.phy_2_xgmii_txd(qsfp3_txd_2_int),
|
|
.phy_2_xgmii_txc(qsfp3_txc_2_int),
|
|
.phy_2_rx_clk(qsfp3_rx_clk_2_int),
|
|
.phy_2_rx_rst(qsfp3_rx_rst_2_int),
|
|
.phy_2_xgmii_rxd(qsfp3_rxd_2_int),
|
|
.phy_2_xgmii_rxc(qsfp3_rxc_2_int),
|
|
.phy_2_rx_block_lock(qsfp3_rx_block_lock_2),
|
|
.phy_2_rx_high_ber(),
|
|
.phy_3_tx_clk(qsfp3_tx_clk_3_int),
|
|
.phy_3_tx_rst(qsfp3_tx_rst_3_int),
|
|
.phy_3_xgmii_txd(qsfp3_txd_3_int),
|
|
.phy_3_xgmii_txc(qsfp3_txc_3_int),
|
|
.phy_3_rx_clk(qsfp3_rx_clk_3_int),
|
|
.phy_3_rx_rst(qsfp3_rx_rst_3_int),
|
|
.phy_3_xgmii_rxd(qsfp3_rxd_3_int),
|
|
.phy_3_xgmii_rxc(qsfp3_rxc_3_int),
|
|
.phy_3_rx_block_lock(qsfp3_rx_block_lock_3),
|
|
.phy_3_rx_high_ber(),
|
|
.phy_4_tx_clk(qsfp3_tx_clk_4_int),
|
|
.phy_4_tx_rst(qsfp3_tx_rst_4_int),
|
|
.phy_4_xgmii_txd(qsfp3_txd_4_int),
|
|
.phy_4_xgmii_txc(qsfp3_txc_4_int),
|
|
.phy_4_rx_clk(qsfp3_rx_clk_4_int),
|
|
.phy_4_rx_rst(qsfp3_rx_rst_4_int),
|
|
.phy_4_xgmii_rxd(qsfp3_rxd_4_int),
|
|
.phy_4_xgmii_rxc(qsfp3_rxc_4_int),
|
|
.phy_4_rx_block_lock(qsfp3_rx_block_lock_4),
|
|
.phy_4_rx_high_ber()
|
|
);
|
|
|
|
assign led_qsfp[0] = qsfp0_rx_block_lock_1;
|
|
assign led_qsfp[1] = qsfp1_rx_block_lock_1;
|
|
assign led_qsfp[2] = qsfp2_rx_block_lock_1;
|
|
assign led_qsfp[3] = qsfp3_rx_block_lock_1;
|
|
|
|
fpga_core
|
|
core_inst (
|
|
/*
|
|
* Clock: 156.25 MHz
|
|
* Synchronous reset
|
|
*/
|
|
.clk(clk_156mhz_int),
|
|
.rst(rst_156mhz_int),
|
|
/*
|
|
* GPIO
|
|
*/
|
|
.led_user_grn(led_user_grn),
|
|
.led_user_red(led_user_red),
|
|
// .led_qsfp(led_qsfp),
|
|
/*
|
|
* Ethernet: QSFP28
|
|
*/
|
|
.qsfp0_tx_clk_1(qsfp0_tx_clk_1_int),
|
|
.qsfp0_tx_rst_1(qsfp0_tx_rst_1_int),
|
|
.qsfp0_txd_1(qsfp0_txd_1_int),
|
|
.qsfp0_txc_1(qsfp0_txc_1_int),
|
|
.qsfp0_rx_clk_1(qsfp0_rx_clk_1_int),
|
|
.qsfp0_rx_rst_1(qsfp0_rx_rst_1_int),
|
|
.qsfp0_rxd_1(qsfp0_rxd_1_int),
|
|
.qsfp0_rxc_1(qsfp0_rxc_1_int),
|
|
.qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
|
|
.qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
|
|
.qsfp0_txd_2(qsfp0_txd_2_int),
|
|
.qsfp0_txc_2(qsfp0_txc_2_int),
|
|
.qsfp0_rx_clk_2(qsfp0_rx_clk_2_int),
|
|
.qsfp0_rx_rst_2(qsfp0_rx_rst_2_int),
|
|
.qsfp0_rxd_2(qsfp0_rxd_2_int),
|
|
.qsfp0_rxc_2(qsfp0_rxc_2_int),
|
|
.qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
|
|
.qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
|
|
.qsfp0_txd_3(qsfp0_txd_3_int),
|
|
.qsfp0_txc_3(qsfp0_txc_3_int),
|
|
.qsfp0_rx_clk_3(qsfp0_rx_clk_3_int),
|
|
.qsfp0_rx_rst_3(qsfp0_rx_rst_3_int),
|
|
.qsfp0_rxd_3(qsfp0_rxd_3_int),
|
|
.qsfp0_rxc_3(qsfp0_rxc_3_int),
|
|
.qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
|
|
.qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
|
|
.qsfp0_txd_4(qsfp0_txd_4_int),
|
|
.qsfp0_txc_4(qsfp0_txc_4_int),
|
|
.qsfp0_rx_clk_4(qsfp0_rx_clk_4_int),
|
|
.qsfp0_rx_rst_4(qsfp0_rx_rst_4_int),
|
|
.qsfp0_rxd_4(qsfp0_rxd_4_int),
|
|
.qsfp0_rxc_4(qsfp0_rxc_4_int),
|
|
.qsfp1_tx_clk_1(qsfp1_tx_clk_1_int),
|
|
.qsfp1_tx_rst_1(qsfp1_tx_rst_1_int),
|
|
.qsfp1_txd_1(qsfp1_txd_1_int),
|
|
.qsfp1_txc_1(qsfp1_txc_1_int),
|
|
.qsfp1_rx_clk_1(qsfp1_rx_clk_1_int),
|
|
.qsfp1_rx_rst_1(qsfp1_rx_rst_1_int),
|
|
.qsfp1_rxd_1(qsfp1_rxd_1_int),
|
|
.qsfp1_rxc_1(qsfp1_rxc_1_int),
|
|
.qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
|
|
.qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
|
|
.qsfp1_txd_2(qsfp1_txd_2_int),
|
|
.qsfp1_txc_2(qsfp1_txc_2_int),
|
|
.qsfp1_rx_clk_2(qsfp1_rx_clk_2_int),
|
|
.qsfp1_rx_rst_2(qsfp1_rx_rst_2_int),
|
|
.qsfp1_rxd_2(qsfp1_rxd_2_int),
|
|
.qsfp1_rxc_2(qsfp1_rxc_2_int),
|
|
.qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
|
|
.qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
|
|
.qsfp1_txd_3(qsfp1_txd_3_int),
|
|
.qsfp1_txc_3(qsfp1_txc_3_int),
|
|
.qsfp1_rx_clk_3(qsfp1_rx_clk_3_int),
|
|
.qsfp1_rx_rst_3(qsfp1_rx_rst_3_int),
|
|
.qsfp1_rxd_3(qsfp1_rxd_3_int),
|
|
.qsfp1_rxc_3(qsfp1_rxc_3_int),
|
|
.qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
|
|
.qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
|
|
.qsfp1_txd_4(qsfp1_txd_4_int),
|
|
.qsfp1_txc_4(qsfp1_txc_4_int),
|
|
.qsfp1_rx_clk_4(qsfp1_rx_clk_4_int),
|
|
.qsfp1_rx_rst_4(qsfp1_rx_rst_4_int),
|
|
.qsfp1_rxd_4(qsfp1_rxd_4_int),
|
|
.qsfp1_rxc_4(qsfp1_rxc_4_int),
|
|
.qsfp2_tx_clk_1(qsfp2_tx_clk_1_int),
|
|
.qsfp2_tx_rst_1(qsfp2_tx_rst_1_int),
|
|
.qsfp2_txd_1(qsfp2_txd_1_int),
|
|
.qsfp2_txc_1(qsfp2_txc_1_int),
|
|
.qsfp2_rx_clk_1(qsfp2_rx_clk_1_int),
|
|
.qsfp2_rx_rst_1(qsfp2_rx_rst_1_int),
|
|
.qsfp2_rxd_1(qsfp2_rxd_1_int),
|
|
.qsfp2_rxc_1(qsfp2_rxc_1_int),
|
|
.qsfp2_tx_clk_2(qsfp2_tx_clk_2_int),
|
|
.qsfp2_tx_rst_2(qsfp2_tx_rst_2_int),
|
|
.qsfp2_txd_2(qsfp2_txd_2_int),
|
|
.qsfp2_txc_2(qsfp2_txc_2_int),
|
|
.qsfp2_rx_clk_2(qsfp2_rx_clk_2_int),
|
|
.qsfp2_rx_rst_2(qsfp2_rx_rst_2_int),
|
|
.qsfp2_rxd_2(qsfp2_rxd_2_int),
|
|
.qsfp2_rxc_2(qsfp2_rxc_2_int),
|
|
.qsfp2_tx_clk_3(qsfp2_tx_clk_3_int),
|
|
.qsfp2_tx_rst_3(qsfp2_tx_rst_3_int),
|
|
.qsfp2_txd_3(qsfp2_txd_3_int),
|
|
.qsfp2_txc_3(qsfp2_txc_3_int),
|
|
.qsfp2_rx_clk_3(qsfp2_rx_clk_3_int),
|
|
.qsfp2_rx_rst_3(qsfp2_rx_rst_3_int),
|
|
.qsfp2_rxd_3(qsfp2_rxd_3_int),
|
|
.qsfp2_rxc_3(qsfp2_rxc_3_int),
|
|
.qsfp2_tx_clk_4(qsfp2_tx_clk_4_int),
|
|
.qsfp2_tx_rst_4(qsfp2_tx_rst_4_int),
|
|
.qsfp2_txd_4(qsfp2_txd_4_int),
|
|
.qsfp2_txc_4(qsfp2_txc_4_int),
|
|
.qsfp2_rx_clk_4(qsfp2_rx_clk_4_int),
|
|
.qsfp2_rx_rst_4(qsfp2_rx_rst_4_int),
|
|
.qsfp2_rxd_4(qsfp2_rxd_4_int),
|
|
.qsfp2_rxc_4(qsfp2_rxc_4_int),
|
|
.qsfp3_tx_clk_1(qsfp3_tx_clk_1_int),
|
|
.qsfp3_tx_rst_1(qsfp3_tx_rst_1_int),
|
|
.qsfp3_txd_1(qsfp3_txd_1_int),
|
|
.qsfp3_txc_1(qsfp3_txc_1_int),
|
|
.qsfp3_rx_clk_1(qsfp3_rx_clk_1_int),
|
|
.qsfp3_rx_rst_1(qsfp3_rx_rst_1_int),
|
|
.qsfp3_rxd_1(qsfp3_rxd_1_int),
|
|
.qsfp3_rxc_1(qsfp3_rxc_1_int),
|
|
.qsfp3_tx_clk_2(qsfp3_tx_clk_2_int),
|
|
.qsfp3_tx_rst_2(qsfp3_tx_rst_2_int),
|
|
.qsfp3_txd_2(qsfp3_txd_2_int),
|
|
.qsfp3_txc_2(qsfp3_txc_2_int),
|
|
.qsfp3_rx_clk_2(qsfp3_rx_clk_2_int),
|
|
.qsfp3_rx_rst_2(qsfp3_rx_rst_2_int),
|
|
.qsfp3_rxd_2(qsfp3_rxd_2_int),
|
|
.qsfp3_rxc_2(qsfp3_rxc_2_int),
|
|
.qsfp3_tx_clk_3(qsfp3_tx_clk_3_int),
|
|
.qsfp3_tx_rst_3(qsfp3_tx_rst_3_int),
|
|
.qsfp3_txd_3(qsfp3_txd_3_int),
|
|
.qsfp3_txc_3(qsfp3_txc_3_int),
|
|
.qsfp3_rx_clk_3(qsfp3_rx_clk_3_int),
|
|
.qsfp3_rx_rst_3(qsfp3_rx_rst_3_int),
|
|
.qsfp3_rxd_3(qsfp3_rxd_3_int),
|
|
.qsfp3_rxc_3(qsfp3_rxc_3_int),
|
|
.qsfp3_tx_clk_4(qsfp3_tx_clk_4_int),
|
|
.qsfp3_tx_rst_4(qsfp3_tx_rst_4_int),
|
|
.qsfp3_txd_4(qsfp3_txd_4_int),
|
|
.qsfp3_txc_4(qsfp3_txc_4_int),
|
|
.qsfp3_rx_clk_4(qsfp3_rx_clk_4_int),
|
|
.qsfp3_rx_rst_4(qsfp3_rx_rst_4_int),
|
|
.qsfp3_rxd_4(qsfp3_rxd_4_int),
|
|
.qsfp3_rxc_4(qsfp3_rxc_4_int)
|
|
);
|
|
|
|
endmodule
|
|
|
|
`resetall
|