mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-28 07:03:08 +08:00
682 lines
19 KiB
Verilog
682 lines
19 KiB
Verilog
/*
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Copyright (c) 2020 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA core logic
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*/
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module fpga_core #
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(
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parameter TARGET = "GENERIC"
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)
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(
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/*
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* Clock: 125MHz
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* Synchronous reset
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*/
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input wire clk,
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input wire clk90,
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input wire rst,
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/*
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* GPIO
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*/
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input wire [3:0] btn,
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input wire [17:0] sw,
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output wire [8:0] ledg,
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output wire [17:0] ledr,
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output wire [6:0] hex0,
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output wire [6:0] hex1,
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output wire [6:0] hex2,
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output wire [6:0] hex3,
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output wire [6:0] hex4,
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output wire [6:0] hex5,
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output wire [6:0] hex6,
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output wire [6:0] hex7,
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output wire [35:0] gpio,
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/*
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* Ethernet: 1000BASE-T RGMII
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*/
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input wire phy0_rx_clk,
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input wire [3:0] phy0_rxd,
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input wire phy0_rx_ctl,
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output wire phy0_tx_clk,
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output wire [3:0] phy0_txd,
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output wire phy0_tx_ctl,
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output wire phy0_reset_n,
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input wire phy0_int_n,
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input wire phy1_rx_clk,
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input wire [3:0] phy1_rxd,
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input wire phy1_rx_ctl,
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output wire phy1_tx_clk,
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output wire [3:0] phy1_txd,
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output wire phy1_tx_ctl,
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output wire phy1_reset_n,
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input wire phy1_int_n
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);
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// AXI between MAC and Ethernet modules
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wire [7:0] rx_axis_tdata;
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wire rx_axis_tvalid;
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wire rx_axis_tready;
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wire rx_axis_tlast;
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wire rx_axis_tuser;
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wire [7:0] tx_axis_tdata;
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wire tx_axis_tvalid;
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wire tx_axis_tready;
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wire tx_axis_tlast;
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wire tx_axis_tuser;
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// Ethernet frame between Ethernet modules and UDP stack
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wire rx_eth_hdr_ready;
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wire rx_eth_hdr_valid;
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wire [47:0] rx_eth_dest_mac;
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wire [47:0] rx_eth_src_mac;
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wire [15:0] rx_eth_type;
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wire [7:0] rx_eth_payload_axis_tdata;
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wire rx_eth_payload_axis_tvalid;
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wire rx_eth_payload_axis_tready;
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wire rx_eth_payload_axis_tlast;
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wire rx_eth_payload_axis_tuser;
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wire tx_eth_hdr_ready;
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wire tx_eth_hdr_valid;
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wire [47:0] tx_eth_dest_mac;
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wire [47:0] tx_eth_src_mac;
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wire [15:0] tx_eth_type;
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wire [7:0] tx_eth_payload_axis_tdata;
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wire tx_eth_payload_axis_tvalid;
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wire tx_eth_payload_axis_tready;
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wire tx_eth_payload_axis_tlast;
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wire tx_eth_payload_axis_tuser;
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// IP frame connections
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wire rx_ip_hdr_valid;
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wire rx_ip_hdr_ready;
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wire [47:0] rx_ip_eth_dest_mac;
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wire [47:0] rx_ip_eth_src_mac;
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wire [15:0] rx_ip_eth_type;
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wire [3:0] rx_ip_version;
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wire [3:0] rx_ip_ihl;
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wire [5:0] rx_ip_dscp;
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wire [1:0] rx_ip_ecn;
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wire [15:0] rx_ip_length;
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wire [15:0] rx_ip_identification;
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wire [2:0] rx_ip_flags;
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wire [12:0] rx_ip_fragment_offset;
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wire [7:0] rx_ip_ttl;
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wire [7:0] rx_ip_protocol;
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wire [15:0] rx_ip_header_checksum;
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wire [31:0] rx_ip_source_ip;
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wire [31:0] rx_ip_dest_ip;
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wire [7:0] rx_ip_payload_axis_tdata;
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wire rx_ip_payload_axis_tvalid;
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wire rx_ip_payload_axis_tready;
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wire rx_ip_payload_axis_tlast;
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wire rx_ip_payload_axis_tuser;
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wire tx_ip_hdr_valid;
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wire tx_ip_hdr_ready;
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wire [5:0] tx_ip_dscp;
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wire [1:0] tx_ip_ecn;
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wire [15:0] tx_ip_length;
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wire [7:0] tx_ip_ttl;
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wire [7:0] tx_ip_protocol;
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wire [31:0] tx_ip_source_ip;
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wire [31:0] tx_ip_dest_ip;
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wire [7:0] tx_ip_payload_axis_tdata;
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wire tx_ip_payload_axis_tvalid;
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wire tx_ip_payload_axis_tready;
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wire tx_ip_payload_axis_tlast;
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wire tx_ip_payload_axis_tuser;
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// UDP frame connections
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wire rx_udp_hdr_valid;
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wire rx_udp_hdr_ready;
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wire [47:0] rx_udp_eth_dest_mac;
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wire [47:0] rx_udp_eth_src_mac;
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wire [15:0] rx_udp_eth_type;
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wire [3:0] rx_udp_ip_version;
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wire [3:0] rx_udp_ip_ihl;
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wire [5:0] rx_udp_ip_dscp;
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wire [1:0] rx_udp_ip_ecn;
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wire [15:0] rx_udp_ip_length;
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wire [15:0] rx_udp_ip_identification;
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wire [2:0] rx_udp_ip_flags;
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wire [12:0] rx_udp_ip_fragment_offset;
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wire [7:0] rx_udp_ip_ttl;
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wire [7:0] rx_udp_ip_protocol;
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wire [15:0] rx_udp_ip_header_checksum;
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wire [31:0] rx_udp_ip_source_ip;
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wire [31:0] rx_udp_ip_dest_ip;
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wire [15:0] rx_udp_source_port;
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wire [15:0] rx_udp_dest_port;
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wire [15:0] rx_udp_length;
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wire [15:0] rx_udp_checksum;
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wire [7:0] rx_udp_payload_axis_tdata;
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wire rx_udp_payload_axis_tvalid;
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wire rx_udp_payload_axis_tready;
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wire rx_udp_payload_axis_tlast;
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wire rx_udp_payload_axis_tuser;
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wire tx_udp_hdr_valid;
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wire tx_udp_hdr_ready;
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wire [5:0] tx_udp_ip_dscp;
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wire [1:0] tx_udp_ip_ecn;
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wire [7:0] tx_udp_ip_ttl;
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wire [31:0] tx_udp_ip_source_ip;
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wire [31:0] tx_udp_ip_dest_ip;
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wire [15:0] tx_udp_source_port;
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wire [15:0] tx_udp_dest_port;
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wire [15:0] tx_udp_length;
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wire [15:0] tx_udp_checksum;
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wire [7:0] tx_udp_payload_axis_tdata;
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wire tx_udp_payload_axis_tvalid;
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wire tx_udp_payload_axis_tready;
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wire tx_udp_payload_axis_tlast;
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wire tx_udp_payload_axis_tuser;
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wire [7:0] rx_fifo_udp_payload_axis_tdata;
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wire rx_fifo_udp_payload_axis_tvalid;
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wire rx_fifo_udp_payload_axis_tready;
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wire rx_fifo_udp_payload_axis_tlast;
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wire rx_fifo_udp_payload_axis_tuser;
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wire [7:0] tx_fifo_udp_payload_axis_tdata;
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wire tx_fifo_udp_payload_axis_tvalid;
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wire tx_fifo_udp_payload_axis_tready;
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wire tx_fifo_udp_payload_axis_tlast;
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wire tx_fifo_udp_payload_axis_tuser;
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// Configuration
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wire [47:0] local_mac = 48'h02_00_00_00_00_00;
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wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
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wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
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wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
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// IP ports not used
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assign rx_ip_hdr_ready = 1;
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assign rx_ip_payload_axis_tready = 1;
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assign tx_ip_hdr_valid = 0;
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assign tx_ip_dscp = 0;
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assign tx_ip_ecn = 0;
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assign tx_ip_length = 0;
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assign tx_ip_ttl = 0;
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assign tx_ip_protocol = 0;
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assign tx_ip_source_ip = 0;
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assign tx_ip_dest_ip = 0;
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assign tx_ip_payload_axis_tdata = 0;
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assign tx_ip_payload_axis_tvalid = 0;
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assign tx_ip_payload_axis_tlast = 0;
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assign tx_ip_payload_axis_tuser = 0;
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// Loop back UDP
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wire match_cond = rx_udp_dest_port == 1234;
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wire no_match = !match_cond;
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reg match_cond_reg = 0;
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reg no_match_reg = 0;
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always @(posedge clk) begin
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if (rst) begin
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match_cond_reg <= 0;
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no_match_reg <= 0;
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end else begin
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if (rx_udp_payload_axis_tvalid) begin
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if ((!match_cond_reg && !no_match_reg) ||
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(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
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match_cond_reg <= match_cond;
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no_match_reg <= no_match;
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end
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end else begin
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match_cond_reg <= 0;
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no_match_reg <= 0;
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end
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end
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end
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assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
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assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
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assign tx_udp_ip_dscp = 0;
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assign tx_udp_ip_ecn = 0;
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assign tx_udp_ip_ttl = 64;
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assign tx_udp_ip_source_ip = local_ip;
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assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
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assign tx_udp_source_port = rx_udp_dest_port;
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assign tx_udp_dest_port = rx_udp_source_port;
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assign tx_udp_length = rx_udp_length;
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assign tx_udp_checksum = 0;
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assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
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assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
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assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
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assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
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assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
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assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
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assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
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assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
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assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
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assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
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// Place first payload byte onto LEDs
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reg valid_last = 0;
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reg [7:0] led_reg = 0;
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always @(posedge clk) begin
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if (tx_udp_payload_axis_tvalid) begin
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if (!valid_last) begin
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led_reg <= tx_udp_payload_axis_tdata;
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valid_last <= 1'b1;
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end
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if (tx_udp_payload_axis_tlast) begin
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valid_last <= 1'b0;
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end
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end
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if (rst) begin
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led_reg <= 0;
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end
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end
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// place dest IP onto 7 segment displays
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reg [31:0] dest_ip_reg = 0;
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always @(posedge clk) begin
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if (tx_udp_hdr_valid) begin
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dest_ip_reg <= tx_udp_ip_dest_ip;
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end
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if (rst) begin
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dest_ip_reg <= 0;
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end
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end
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hex_display #(
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.INVERT(1)
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)
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hex_display_0 (
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.in(dest_ip_reg[3:0]),
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.enable(1),
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.out(hex0)
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);
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hex_display #(
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.INVERT(1)
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)
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hex_display_1 (
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.in(dest_ip_reg[7:4]),
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.enable(1),
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.out(hex1)
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);
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hex_display #(
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.INVERT(1)
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)
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hex_display_2 (
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.in(dest_ip_reg[11:8]),
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.enable(1),
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.out(hex2)
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);
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hex_display #(
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.INVERT(1)
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)
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hex_display_3 (
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.in(dest_ip_reg[15:12]),
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.enable(1),
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.out(hex3)
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);
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hex_display #(
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.INVERT(1)
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)
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hex_display_4 (
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.in(dest_ip_reg[19:16]),
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.enable(1),
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.out(hex4)
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);
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hex_display #(
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.INVERT(1)
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)
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hex_display_5 (
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.in(dest_ip_reg[23:20]),
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.enable(1),
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.out(hex5)
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);
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hex_display #(
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.INVERT(1)
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)
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hex_display_6 (
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.in(dest_ip_reg[27:24]),
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.enable(1),
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.out(hex6)
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);
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hex_display #(
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.INVERT(1)
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)
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hex_display_7 (
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.in(dest_ip_reg[31:28]),
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.enable(1),
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.out(hex7)
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);
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//assign led = sw;
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assign ledg = led_reg;
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assign ledr = sw;
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assign phy0_reset_n = ~rst;
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assign phy1_reset_n = ~rst;
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assign gpio = 0;
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eth_mac_1g_rgmii_fifo #(
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.TARGET(TARGET),
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.USE_CLK90("TRUE"),
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.ENABLE_PADDING(1),
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.MIN_FRAME_LENGTH(64),
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.TX_FIFO_DEPTH(4096),
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.TX_FRAME_FIFO(1),
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.RX_FIFO_DEPTH(4096),
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.RX_FRAME_FIFO(1)
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)
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eth_mac_inst (
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.gtx_clk(clk),
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.gtx_clk90(clk90),
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.gtx_rst(rst),
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.logic_clk(clk),
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.logic_rst(rst),
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.tx_axis_tdata(tx_axis_tdata),
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.tx_axis_tvalid(tx_axis_tvalid),
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.tx_axis_tready(tx_axis_tready),
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.tx_axis_tlast(tx_axis_tlast),
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.tx_axis_tuser(tx_axis_tuser),
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.rx_axis_tdata(rx_axis_tdata),
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.rx_axis_tvalid(rx_axis_tvalid),
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.rx_axis_tready(rx_axis_tready),
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.rx_axis_tlast(rx_axis_tlast),
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.rx_axis_tuser(rx_axis_tuser),
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.rgmii_rx_clk(phy0_rx_clk),
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.rgmii_rxd(phy0_rxd),
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.rgmii_rx_ctl(phy0_rx_ctl),
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.rgmii_tx_clk(phy0_tx_clk),
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.rgmii_txd(phy0_txd),
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.rgmii_tx_ctl(phy0_tx_ctl),
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.tx_fifo_overflow(),
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.tx_fifo_bad_frame(),
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.tx_fifo_good_frame(),
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.rx_error_bad_frame(),
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.rx_error_bad_fcs(),
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.rx_fifo_overflow(),
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.rx_fifo_bad_frame(),
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.rx_fifo_good_frame(),
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.speed(),
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.cfg_ifg(8'd12),
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.cfg_tx_enable(1'b1),
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.cfg_rx_enable(1'b1)
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);
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eth_axis_rx
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eth_axis_rx_inst (
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.clk(clk),
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.rst(rst),
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// AXI input
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.s_axis_tdata(rx_axis_tdata),
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.s_axis_tvalid(rx_axis_tvalid),
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.s_axis_tready(rx_axis_tready),
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.s_axis_tlast(rx_axis_tlast),
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.s_axis_tuser(rx_axis_tuser),
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// Ethernet frame output
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.m_eth_hdr_valid(rx_eth_hdr_valid),
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.m_eth_hdr_ready(rx_eth_hdr_ready),
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.m_eth_dest_mac(rx_eth_dest_mac),
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.m_eth_src_mac(rx_eth_src_mac),
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.m_eth_type(rx_eth_type),
|
|
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
|
|
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
|
|
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
|
|
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
|
|
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
|
|
// Status signals
|
|
.busy(),
|
|
.error_header_early_termination()
|
|
);
|
|
|
|
eth_axis_tx
|
|
eth_axis_tx_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
// Ethernet frame input
|
|
.s_eth_hdr_valid(tx_eth_hdr_valid),
|
|
.s_eth_hdr_ready(tx_eth_hdr_ready),
|
|
.s_eth_dest_mac(tx_eth_dest_mac),
|
|
.s_eth_src_mac(tx_eth_src_mac),
|
|
.s_eth_type(tx_eth_type),
|
|
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
|
|
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
|
|
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
|
|
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
|
|
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
|
|
// AXI output
|
|
.m_axis_tdata(tx_axis_tdata),
|
|
.m_axis_tvalid(tx_axis_tvalid),
|
|
.m_axis_tready(tx_axis_tready),
|
|
.m_axis_tlast(tx_axis_tlast),
|
|
.m_axis_tuser(tx_axis_tuser),
|
|
// Status signals
|
|
.busy()
|
|
);
|
|
|
|
udp_complete
|
|
udp_complete_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
// Ethernet frame input
|
|
.s_eth_hdr_valid(rx_eth_hdr_valid),
|
|
.s_eth_hdr_ready(rx_eth_hdr_ready),
|
|
.s_eth_dest_mac(rx_eth_dest_mac),
|
|
.s_eth_src_mac(rx_eth_src_mac),
|
|
.s_eth_type(rx_eth_type),
|
|
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
|
|
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
|
|
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
|
|
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
|
|
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
|
|
// Ethernet frame output
|
|
.m_eth_hdr_valid(tx_eth_hdr_valid),
|
|
.m_eth_hdr_ready(tx_eth_hdr_ready),
|
|
.m_eth_dest_mac(tx_eth_dest_mac),
|
|
.m_eth_src_mac(tx_eth_src_mac),
|
|
.m_eth_type(tx_eth_type),
|
|
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
|
|
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
|
|
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
|
|
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
|
|
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
|
|
// IP frame input
|
|
.s_ip_hdr_valid(tx_ip_hdr_valid),
|
|
.s_ip_hdr_ready(tx_ip_hdr_ready),
|
|
.s_ip_dscp(tx_ip_dscp),
|
|
.s_ip_ecn(tx_ip_ecn),
|
|
.s_ip_length(tx_ip_length),
|
|
.s_ip_ttl(tx_ip_ttl),
|
|
.s_ip_protocol(tx_ip_protocol),
|
|
.s_ip_source_ip(tx_ip_source_ip),
|
|
.s_ip_dest_ip(tx_ip_dest_ip),
|
|
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
|
|
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
|
|
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
|
|
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
|
|
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
|
|
// IP frame output
|
|
.m_ip_hdr_valid(rx_ip_hdr_valid),
|
|
.m_ip_hdr_ready(rx_ip_hdr_ready),
|
|
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
|
|
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
|
|
.m_ip_eth_type(rx_ip_eth_type),
|
|
.m_ip_version(rx_ip_version),
|
|
.m_ip_ihl(rx_ip_ihl),
|
|
.m_ip_dscp(rx_ip_dscp),
|
|
.m_ip_ecn(rx_ip_ecn),
|
|
.m_ip_length(rx_ip_length),
|
|
.m_ip_identification(rx_ip_identification),
|
|
.m_ip_flags(rx_ip_flags),
|
|
.m_ip_fragment_offset(rx_ip_fragment_offset),
|
|
.m_ip_ttl(rx_ip_ttl),
|
|
.m_ip_protocol(rx_ip_protocol),
|
|
.m_ip_header_checksum(rx_ip_header_checksum),
|
|
.m_ip_source_ip(rx_ip_source_ip),
|
|
.m_ip_dest_ip(rx_ip_dest_ip),
|
|
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
|
|
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
|
|
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
|
|
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
|
|
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
|
|
// UDP frame input
|
|
.s_udp_hdr_valid(tx_udp_hdr_valid),
|
|
.s_udp_hdr_ready(tx_udp_hdr_ready),
|
|
.s_udp_ip_dscp(tx_udp_ip_dscp),
|
|
.s_udp_ip_ecn(tx_udp_ip_ecn),
|
|
.s_udp_ip_ttl(tx_udp_ip_ttl),
|
|
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
|
|
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
|
|
.s_udp_source_port(tx_udp_source_port),
|
|
.s_udp_dest_port(tx_udp_dest_port),
|
|
.s_udp_length(tx_udp_length),
|
|
.s_udp_checksum(tx_udp_checksum),
|
|
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
|
|
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
|
|
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
|
|
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
|
|
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
|
|
// UDP frame output
|
|
.m_udp_hdr_valid(rx_udp_hdr_valid),
|
|
.m_udp_hdr_ready(rx_udp_hdr_ready),
|
|
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
|
|
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
|
|
.m_udp_eth_type(rx_udp_eth_type),
|
|
.m_udp_ip_version(rx_udp_ip_version),
|
|
.m_udp_ip_ihl(rx_udp_ip_ihl),
|
|
.m_udp_ip_dscp(rx_udp_ip_dscp),
|
|
.m_udp_ip_ecn(rx_udp_ip_ecn),
|
|
.m_udp_ip_length(rx_udp_ip_length),
|
|
.m_udp_ip_identification(rx_udp_ip_identification),
|
|
.m_udp_ip_flags(rx_udp_ip_flags),
|
|
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
|
|
.m_udp_ip_ttl(rx_udp_ip_ttl),
|
|
.m_udp_ip_protocol(rx_udp_ip_protocol),
|
|
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
|
|
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
|
|
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
|
|
.m_udp_source_port(rx_udp_source_port),
|
|
.m_udp_dest_port(rx_udp_dest_port),
|
|
.m_udp_length(rx_udp_length),
|
|
.m_udp_checksum(rx_udp_checksum),
|
|
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
|
|
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
|
|
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
|
|
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
|
|
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
|
|
// Status signals
|
|
.ip_rx_busy(),
|
|
.ip_tx_busy(),
|
|
.udp_rx_busy(),
|
|
.udp_tx_busy(),
|
|
.ip_rx_error_header_early_termination(),
|
|
.ip_rx_error_payload_early_termination(),
|
|
.ip_rx_error_invalid_header(),
|
|
.ip_rx_error_invalid_checksum(),
|
|
.ip_tx_error_payload_early_termination(),
|
|
.ip_tx_error_arp_failed(),
|
|
.udp_rx_error_header_early_termination(),
|
|
.udp_rx_error_payload_early_termination(),
|
|
.udp_tx_error_payload_early_termination(),
|
|
// Configuration
|
|
.local_mac(local_mac),
|
|
.local_ip(local_ip),
|
|
.gateway_ip(gateway_ip),
|
|
.subnet_mask(subnet_mask),
|
|
.clear_arp_cache(0)
|
|
);
|
|
|
|
axis_fifo #(
|
|
.DEPTH(8192),
|
|
.DATA_WIDTH(8),
|
|
.KEEP_ENABLE(0),
|
|
.ID_ENABLE(0),
|
|
.DEST_ENABLE(0),
|
|
.USER_ENABLE(1),
|
|
.USER_WIDTH(1),
|
|
.FRAME_FIFO(0)
|
|
)
|
|
udp_payload_fifo (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
// AXI input
|
|
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
|
|
.s_axis_tkeep(0),
|
|
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
|
|
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
|
|
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
|
|
.s_axis_tid(0),
|
|
.s_axis_tdest(0),
|
|
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
|
|
|
|
// AXI output
|
|
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
|
|
.m_axis_tkeep(),
|
|
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
|
|
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
|
|
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
|
|
.m_axis_tid(),
|
|
.m_axis_tdest(),
|
|
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
|
|
|
|
// Status
|
|
.status_overflow(),
|
|
.status_bad_frame(),
|
|
.status_good_frame()
|
|
);
|
|
|
|
endmodule
|
|
|
|
`resetall
|