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verilog-ethernet/example/ExaNIC_X25/fpga_25g/fpga_10g
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Alex Forencich b316c6764e Use quad wrappers in ExaNIC X25 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-08-26 12:44:50 -07:00
..
config.tcl
Use unified 10G/25G design for ExaNIC X25
2023-07-13 20:45:47 -07:00
Makefile
Use quad wrappers in ExaNIC X25 example design
2023-08-26 12:44:50 -07:00