mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-02-04 07:13:13 +08:00
366 lines
11 KiB
Verilog
366 lines
11 KiB
Verilog
/*
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga (
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/*
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* Clock: 100 MHz
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* Reset: Push button, active low
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*/
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input wire clk_sys_100m_p,
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input wire cpu_resetn,
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/*
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* GPIO
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*/
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output wire [3:0] user_led,
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/*
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* Ethernet: QSFP28
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*/
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output wire [3:0] qsfp0_tx_p,
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input wire [3:0] qsfp0_rx_p,
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input wire refclk_qsfp0_p,
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output wire qsfp0_modsel_l,
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output wire qsfp0_reset_l,
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input wire qsfp0_modprs_l,
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output wire qsfp0_lpmode,
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input wire qsfp0_int_l,
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output wire [3:0] qsfp1_tx_p,
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input wire [3:0] qsfp1_rx_p,
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input wire refclk_qsfp1_p,
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output wire qsfp1_modsel_l,
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output wire qsfp1_reset_l,
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input wire qsfp1_modprs_l,
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output wire qsfp1_lpmode,
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input wire qsfp1_int_l
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);
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// Clock and reset
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wire ninit_done;
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reset_release reset_release_inst (
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.ninit_done (ninit_done)
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);
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wire clk_100mhz = clk_sys_100m_p;
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wire rst_100mhz;
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sync_reset #(
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.N(4)
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)
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sync_reset_100mhz_inst (
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.clk(clk_100mhz),
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.rst(~cpu_resetn || ninit_done),
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.out(rst_100mhz)
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);
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wire clk_156mhz_int;
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wire rst_156mhz_int;
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// XGMII 10G PHY
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// QSFP0
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assign qsfp0_modsel_l = 1'b0;
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assign qsfp0_reset_l = 1'b1;
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assign qsfp0_lpmode = 1'b0;
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wire qsfp0_tx_clk_1_int;
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wire qsfp0_tx_rst_1_int;
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wire [63:0] qsfp0_txd_1_int;
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wire [7:0] qsfp0_txc_1_int;
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wire qsfp0_rx_clk_1_int;
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wire qsfp0_rx_rst_1_int;
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wire [63:0] qsfp0_rxd_1_int;
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wire [7:0] qsfp0_rxc_1_int;
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wire qsfp0_tx_clk_2_int;
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wire qsfp0_tx_rst_2_int;
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wire [63:0] qsfp0_txd_2_int;
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wire [7:0] qsfp0_txc_2_int;
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wire qsfp0_rx_clk_2_int;
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wire qsfp0_rx_rst_2_int;
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wire [63:0] qsfp0_rxd_2_int;
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wire [7:0] qsfp0_rxc_2_int;
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wire qsfp0_tx_clk_3_int;
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wire qsfp0_tx_rst_3_int;
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wire [63:0] qsfp0_txd_3_int;
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wire [7:0] qsfp0_txc_3_int;
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wire qsfp0_rx_clk_3_int;
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wire qsfp0_rx_rst_3_int;
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wire [63:0] qsfp0_rxd_3_int;
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wire [7:0] qsfp0_rxc_3_int;
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wire qsfp0_tx_clk_4_int;
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wire qsfp0_tx_rst_4_int;
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wire [63:0] qsfp0_txd_4_int;
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wire [7:0] qsfp0_txc_4_int;
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wire qsfp0_rx_clk_4_int;
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wire qsfp0_rx_rst_4_int;
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wire [63:0] qsfp0_rxd_4_int;
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wire [7:0] qsfp0_rxc_4_int;
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assign clk_156mhz_int = qsfp0_tx_clk_1_int;
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assign rst_156mhz_int = qsfp0_tx_rst_1_int;
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wire qsfp0_rx_block_lock_1;
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wire qsfp0_rx_block_lock_2;
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wire qsfp0_rx_block_lock_3;
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wire qsfp0_rx_block_lock_4;
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eth_xcvr_phy_quad_wrapper qsfp0_eth_xcvr_phy_quad (
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.xcvr_ctrl_clk(clk_100mhz),
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.xcvr_ctrl_rst(rst_100mhz),
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.xcvr_ref_clk(refclk_qsfp0_p),
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.xcvr_tx_serial_data(qsfp0_tx_p),
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.xcvr_rx_serial_data(qsfp0_rx_p),
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.phy_1_tx_clk(qsfp0_tx_clk_1_int),
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.phy_1_tx_rst(qsfp0_tx_rst_1_int),
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.phy_1_xgmii_txd(qsfp0_txd_1_int),
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.phy_1_xgmii_txc(qsfp0_txc_1_int),
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.phy_1_rx_clk(qsfp0_rx_clk_1_int),
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.phy_1_rx_rst(qsfp0_rx_rst_1_int),
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.phy_1_xgmii_rxd(qsfp0_rxd_1_int),
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.phy_1_xgmii_rxc(qsfp0_rxc_1_int),
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.phy_1_rx_block_lock(qsfp0_rx_block_lock_1),
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.phy_1_rx_high_ber(),
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.phy_2_tx_clk(qsfp0_tx_clk_2_int),
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.phy_2_tx_rst(qsfp0_tx_rst_2_int),
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.phy_2_xgmii_txd(qsfp0_txd_2_int),
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.phy_2_xgmii_txc(qsfp0_txc_2_int),
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.phy_2_rx_clk(qsfp0_rx_clk_2_int),
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.phy_2_rx_rst(qsfp0_rx_rst_2_int),
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.phy_2_xgmii_rxd(qsfp0_rxd_2_int),
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.phy_2_xgmii_rxc(qsfp0_rxc_2_int),
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.phy_2_rx_block_lock(qsfp0_rx_block_lock_2),
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.phy_2_rx_high_ber(),
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.phy_3_tx_clk(qsfp0_tx_clk_3_int),
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.phy_3_tx_rst(qsfp0_tx_rst_3_int),
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.phy_3_xgmii_txd(qsfp0_txd_3_int),
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.phy_3_xgmii_txc(qsfp0_txc_3_int),
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.phy_3_rx_clk(qsfp0_rx_clk_3_int),
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.phy_3_rx_rst(qsfp0_rx_rst_3_int),
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.phy_3_xgmii_rxd(qsfp0_rxd_3_int),
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.phy_3_xgmii_rxc(qsfp0_rxc_3_int),
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.phy_3_rx_block_lock(qsfp0_rx_block_lock_3),
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.phy_3_rx_high_ber(),
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.phy_4_tx_clk(qsfp0_tx_clk_4_int),
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.phy_4_tx_rst(qsfp0_tx_rst_4_int),
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.phy_4_xgmii_txd(qsfp0_txd_4_int),
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.phy_4_xgmii_txc(qsfp0_txc_4_int),
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.phy_4_rx_clk(qsfp0_rx_clk_4_int),
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.phy_4_rx_rst(qsfp0_rx_rst_4_int),
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.phy_4_xgmii_rxd(qsfp0_rxd_4_int),
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.phy_4_xgmii_rxc(qsfp0_rxc_4_int),
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.phy_4_rx_block_lock(qsfp0_rx_block_lock_4),
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.phy_4_rx_high_ber()
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);
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// QSFP1
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assign qsfp1_modsel_l = 1'b0;
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assign qsfp1_reset_l = 1'b1;
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assign qsfp1_lpmode = 1'b0;
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wire qsfp1_tx_clk_1_int;
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wire qsfp1_tx_rst_1_int;
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wire [63:0] qsfp1_txd_1_int;
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wire [7:0] qsfp1_txc_1_int;
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wire qsfp1_rx_clk_1_int;
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wire qsfp1_rx_rst_1_int;
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wire [63:0] qsfp1_rxd_1_int;
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wire [7:0] qsfp1_rxc_1_int;
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wire qsfp1_tx_clk_2_int;
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wire qsfp1_tx_rst_2_int;
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wire [63:0] qsfp1_txd_2_int;
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wire [7:0] qsfp1_txc_2_int;
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wire qsfp1_rx_clk_2_int;
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wire qsfp1_rx_rst_2_int;
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wire [63:0] qsfp1_rxd_2_int;
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wire [7:0] qsfp1_rxc_2_int;
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wire qsfp1_tx_clk_3_int;
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wire qsfp1_tx_rst_3_int;
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wire [63:0] qsfp1_txd_3_int;
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wire [7:0] qsfp1_txc_3_int;
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wire qsfp1_rx_clk_3_int;
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wire qsfp1_rx_rst_3_int;
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wire [63:0] qsfp1_rxd_3_int;
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wire [7:0] qsfp1_rxc_3_int;
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wire qsfp1_tx_clk_4_int;
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wire qsfp1_tx_rst_4_int;
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wire [63:0] qsfp1_txd_4_int;
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wire [7:0] qsfp1_txc_4_int;
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wire qsfp1_rx_clk_4_int;
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wire qsfp1_rx_rst_4_int;
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wire [63:0] qsfp1_rxd_4_int;
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wire [7:0] qsfp1_rxc_4_int;
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wire qsfp1_rx_block_lock_1;
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wire qsfp1_rx_block_lock_2;
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wire qsfp1_rx_block_lock_3;
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wire qsfp1_rx_block_lock_4;
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eth_xcvr_phy_quad_wrapper qsfp1_eth_xcvr_phy_quad (
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.xcvr_ctrl_clk(clk_100mhz),
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.xcvr_ctrl_rst(rst_100mhz),
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.xcvr_ref_clk(refclk_qsfp1_p),
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.xcvr_tx_serial_data(qsfp1_tx_p),
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.xcvr_rx_serial_data(qsfp1_rx_p),
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.phy_1_tx_clk(qsfp1_tx_clk_1_int),
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.phy_1_tx_rst(qsfp1_tx_rst_1_int),
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.phy_1_xgmii_txd(qsfp1_txd_1_int),
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.phy_1_xgmii_txc(qsfp1_txc_1_int),
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.phy_1_rx_clk(qsfp1_rx_clk_1_int),
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.phy_1_rx_rst(qsfp1_rx_rst_1_int),
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.phy_1_xgmii_rxd(qsfp1_rxd_1_int),
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.phy_1_xgmii_rxc(qsfp1_rxc_1_int),
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.phy_1_rx_block_lock(qsfp1_rx_block_lock_1),
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.phy_1_rx_high_ber(),
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.phy_2_tx_clk(qsfp1_tx_clk_2_int),
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.phy_2_tx_rst(qsfp1_tx_rst_2_int),
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.phy_2_xgmii_txd(qsfp1_txd_2_int),
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.phy_2_xgmii_txc(qsfp1_txc_2_int),
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.phy_2_rx_clk(qsfp1_rx_clk_2_int),
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.phy_2_rx_rst(qsfp1_rx_rst_2_int),
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.phy_2_xgmii_rxd(qsfp1_rxd_2_int),
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.phy_2_xgmii_rxc(qsfp1_rxc_2_int),
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.phy_2_rx_block_lock(qsfp1_rx_block_lock_2),
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.phy_2_rx_high_ber(),
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.phy_3_tx_clk(qsfp1_tx_clk_3_int),
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.phy_3_tx_rst(qsfp1_tx_rst_3_int),
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.phy_3_xgmii_txd(qsfp1_txd_3_int),
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.phy_3_xgmii_txc(qsfp1_txc_3_int),
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.phy_3_rx_clk(qsfp1_rx_clk_3_int),
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.phy_3_rx_rst(qsfp1_rx_rst_3_int),
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.phy_3_xgmii_rxd(qsfp1_rxd_3_int),
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.phy_3_xgmii_rxc(qsfp1_rxc_3_int),
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.phy_3_rx_block_lock(qsfp1_rx_block_lock_3),
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.phy_3_rx_high_ber(),
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.phy_4_tx_clk(qsfp1_tx_clk_4_int),
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.phy_4_tx_rst(qsfp1_tx_rst_4_int),
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.phy_4_xgmii_txd(qsfp1_txd_4_int),
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.phy_4_xgmii_txc(qsfp1_txc_4_int),
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.phy_4_rx_clk(qsfp1_rx_clk_4_int),
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.phy_4_rx_rst(qsfp1_rx_rst_4_int),
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.phy_4_xgmii_rxd(qsfp1_rxd_4_int),
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.phy_4_xgmii_rxc(qsfp1_rxc_4_int),
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.phy_4_rx_block_lock(qsfp1_rx_block_lock_4),
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.phy_4_rx_high_ber()
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);
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fpga_core
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core_inst (
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/*
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* Clock: 156.25 MHz
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* Synchronous reset
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*/
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.clk(clk_156mhz_int),
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.rst(rst_156mhz_int),
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/*
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* GPIO
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*/
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.user_led(user_led),
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/*
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* Ethernet: QSFP28
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*/
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.qsfp0_tx_clk_1(qsfp0_tx_clk_1_int),
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.qsfp0_tx_rst_1(qsfp0_tx_rst_1_int),
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.qsfp0_txd_1(qsfp0_txd_1_int),
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.qsfp0_txc_1(qsfp0_txc_1_int),
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.qsfp0_rx_clk_1(qsfp0_rx_clk_1_int),
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.qsfp0_rx_rst_1(qsfp0_rx_rst_1_int),
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.qsfp0_rxd_1(qsfp0_rxd_1_int),
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.qsfp0_rxc_1(qsfp0_rxc_1_int),
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.qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
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.qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
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.qsfp0_txd_2(qsfp0_txd_2_int),
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.qsfp0_txc_2(qsfp0_txc_2_int),
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.qsfp0_rx_clk_2(qsfp0_rx_clk_2_int),
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.qsfp0_rx_rst_2(qsfp0_rx_rst_2_int),
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.qsfp0_rxd_2(qsfp0_rxd_2_int),
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.qsfp0_rxc_2(qsfp0_rxc_2_int),
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.qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
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.qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
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.qsfp0_txd_3(qsfp0_txd_3_int),
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.qsfp0_txc_3(qsfp0_txc_3_int),
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.qsfp0_rx_clk_3(qsfp0_rx_clk_3_int),
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.qsfp0_rx_rst_3(qsfp0_rx_rst_3_int),
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.qsfp0_rxd_3(qsfp0_rxd_3_int),
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.qsfp0_rxc_3(qsfp0_rxc_3_int),
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.qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
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.qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
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.qsfp0_txd_4(qsfp0_txd_4_int),
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.qsfp0_txc_4(qsfp0_txc_4_int),
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.qsfp0_rx_clk_4(qsfp0_rx_clk_4_int),
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.qsfp0_rx_rst_4(qsfp0_rx_rst_4_int),
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.qsfp0_rxd_4(qsfp0_rxd_4_int),
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.qsfp0_rxc_4(qsfp0_rxc_4_int),
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.qsfp1_tx_clk_1(qsfp1_tx_clk_1_int),
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.qsfp1_tx_rst_1(qsfp1_tx_rst_1_int),
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.qsfp1_txd_1(qsfp1_txd_1_int),
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.qsfp1_txc_1(qsfp1_txc_1_int),
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.qsfp1_rx_clk_1(qsfp1_rx_clk_1_int),
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.qsfp1_rx_rst_1(qsfp1_rx_rst_1_int),
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.qsfp1_rxd_1(qsfp1_rxd_1_int),
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.qsfp1_rxc_1(qsfp1_rxc_1_int),
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.qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
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.qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
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.qsfp1_txd_2(qsfp1_txd_2_int),
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.qsfp1_txc_2(qsfp1_txc_2_int),
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.qsfp1_rx_clk_2(qsfp1_rx_clk_2_int),
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.qsfp1_rx_rst_2(qsfp1_rx_rst_2_int),
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.qsfp1_rxd_2(qsfp1_rxd_2_int),
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.qsfp1_rxc_2(qsfp1_rxc_2_int),
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.qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
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.qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
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.qsfp1_txd_3(qsfp1_txd_3_int),
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.qsfp1_txc_3(qsfp1_txc_3_int),
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.qsfp1_rx_clk_3(qsfp1_rx_clk_3_int),
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.qsfp1_rx_rst_3(qsfp1_rx_rst_3_int),
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.qsfp1_rxd_3(qsfp1_rxd_3_int),
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.qsfp1_rxc_3(qsfp1_rxc_3_int),
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.qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
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.qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
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.qsfp1_txd_4(qsfp1_txd_4_int),
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.qsfp1_txc_4(qsfp1_txc_4_int),
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.qsfp1_rx_clk_4(qsfp1_rx_clk_4_int),
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.qsfp1_rx_rst_4(qsfp1_rx_rst_4_int),
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.qsfp1_rxd_4(qsfp1_rxd_4_int),
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.qsfp1_rxc_4(qsfp1_rxc_4_int)
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|
);
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|
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endmodule
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|
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`resetall
|