mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-28 07:03:08 +08:00
308 lines
9.1 KiB
Verilog
308 lines
9.1 KiB
Verilog
/*
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Copyright (c) 2021-2023 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Transceiver and PHY wrapper
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*/
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module eth_xcvr_phy_wrapper #
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(
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parameter HAS_COMMON = 1,
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parameter DATA_WIDTH = 64,
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parameter CTRL_WIDTH = (DATA_WIDTH/8),
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parameter HDR_WIDTH = 2,
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parameter PRBS31_ENABLE = 0,
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parameter TX_SERDES_PIPELINE = 0,
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parameter RX_SERDES_PIPELINE = 0,
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parameter BITSLIP_HIGH_CYCLES = 1,
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parameter BITSLIP_LOW_CYCLES = 8,
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parameter COUNT_125US = 125000/6.4
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)
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(
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input wire xcvr_ctrl_clk,
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input wire xcvr_ctrl_rst,
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/*
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* Common
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*/
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output wire xcvr_gtpowergood_out,
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/*
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* PLL out
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*/
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input wire xcvr_gtrefclk00_in,
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output wire xcvr_qpll0lock_out,
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output wire xcvr_qpll0clk_out,
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output wire xcvr_qpll0refclk_out,
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/*
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* PLL in
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*/
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input wire xcvr_qpll0lock_in,
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output wire xcvr_qpll0reset_out,
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input wire xcvr_qpll0clk_in,
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input wire xcvr_qpll0refclk_in,
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/*
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* Serial data
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*/
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output wire xcvr_txp,
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output wire xcvr_txn,
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input wire xcvr_rxp,
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input wire xcvr_rxn,
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/*
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* PHY connections
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*/
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output wire phy_tx_clk,
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output wire phy_tx_rst,
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input wire [DATA_WIDTH-1:0] phy_xgmii_txd,
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input wire [CTRL_WIDTH-1:0] phy_xgmii_txc,
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output wire phy_rx_clk,
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output wire phy_rx_rst,
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output wire [DATA_WIDTH-1:0] phy_xgmii_rxd,
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output wire [CTRL_WIDTH-1:0] phy_xgmii_rxc,
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output wire phy_tx_bad_block,
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output wire [6:0] phy_rx_error_count,
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output wire phy_rx_bad_block,
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output wire phy_rx_sequence_error,
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output wire phy_rx_block_lock,
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output wire phy_rx_high_ber,
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output wire phy_rx_status,
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input wire phy_cfg_tx_prbs31_enable,
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input wire phy_cfg_rx_prbs31_enable
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);
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wire phy_rx_reset_req;
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wire gt_reset_tx_datapath = 1'b0;
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wire gt_reset_rx_datapath = phy_rx_reset_req;
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wire gt_reset_tx_done;
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wire gt_reset_rx_done;
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wire [5:0] gt_txheader;
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wire [63:0] gt_txdata;
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wire gt_rxgearboxslip;
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wire [5:0] gt_rxheader;
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wire [1:0] gt_rxheadervalid;
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wire [63:0] gt_rxdata;
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wire [1:0] gt_rxdatavalid;
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generate
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if (HAS_COMMON) begin : xcvr
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eth_xcvr_gt_full
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eth_xcvr_gt_full_inst (
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// Common
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.gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk),
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.gtwiz_reset_all_in(xcvr_ctrl_rst),
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.gtpowergood_out(xcvr_gtpowergood_out),
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// PLL
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.gtrefclk00_in(xcvr_gtrefclk00_in),
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.qpll0lock_out(xcvr_qpll0lock_out),
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.qpll0outclk_out(xcvr_qpll0clk_out),
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.qpll0outrefclk_out(xcvr_qpll0refclk_out),
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// Serial data
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.gthtxp_out(xcvr_txp),
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.gthtxn_out(xcvr_txn),
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.gthrxp_in(xcvr_rxp),
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.gthrxn_in(xcvr_rxn),
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// Transmit
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.gtwiz_userclk_tx_reset_in(1'b0),
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.gtwiz_userclk_tx_srcclk_out(),
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.gtwiz_userclk_tx_usrclk_out(),
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.gtwiz_userclk_tx_usrclk2_out(phy_tx_clk),
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.gtwiz_userclk_tx_active_out(),
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.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
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.gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath),
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.gtwiz_reset_tx_done_out(gt_reset_tx_done),
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.txpmaresetdone_out(),
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.txprgdivresetdone_out(),
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.gtwiz_userdata_tx_in(gt_txdata),
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.txheader_in(gt_txheader),
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.txsequence_in(7'b0),
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// Receive
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.gtwiz_userclk_rx_reset_in(1'b0),
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.gtwiz_userclk_rx_srcclk_out(),
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.gtwiz_userclk_rx_usrclk_out(),
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.gtwiz_userclk_rx_usrclk2_out(phy_rx_clk),
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.gtwiz_userclk_rx_active_out(),
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.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
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.gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath),
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.gtwiz_reset_rx_cdr_stable_out(),
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.gtwiz_reset_rx_done_out(gt_reset_rx_done),
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.rxpmaresetdone_out(),
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.rxprgdivresetdone_out(),
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.rxgearboxslip_in(gt_rxgearboxslip),
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.gtwiz_userdata_rx_out(gt_rxdata),
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.rxdatavalid_out(gt_rxdatavalid),
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.rxheader_out(gt_rxheader),
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.rxheadervalid_out(gt_rxheadervalid),
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.rxstartofseq_out()
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);
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assign xcvr_qpll0reset_out = 1'b0;
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end else begin : xcvr
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eth_xcvr_gt_channel
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eth_xcvr_gt_channel_inst (
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// Common
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.gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk),
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.gtwiz_reset_all_in(xcvr_ctrl_rst),
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.gtpowergood_out(xcvr_gtpowergood_out),
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// PLL
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.gtwiz_reset_qpll0lock_in(xcvr_qpll0lock_in),
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.gtwiz_reset_qpll0reset_out(xcvr_qpll0reset_out),
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.qpll0clk_in(xcvr_qpll0clk_in),
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.qpll0refclk_in(xcvr_qpll0refclk_in),
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.qpll1clk_in(1'b0),
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.qpll1refclk_in(1'b0),
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// Serial data
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.gthtxp_out(xcvr_txp),
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.gthtxn_out(xcvr_txn),
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.gthrxp_in(xcvr_rxp),
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.gthrxn_in(xcvr_rxn),
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// Transmit
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.gtwiz_userclk_tx_reset_in(1'b0),
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.gtwiz_userclk_tx_srcclk_out(),
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.gtwiz_userclk_tx_usrclk_out(),
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.gtwiz_userclk_tx_usrclk2_out(phy_tx_clk),
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.gtwiz_userclk_tx_active_out(),
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.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
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.gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath),
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.gtwiz_reset_tx_done_out(gt_reset_tx_done),
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.txpmaresetdone_out(),
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.txprgdivresetdone_out(),
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.gtwiz_userdata_tx_in(gt_txdata),
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.txheader_in(gt_txheader),
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.txsequence_in(7'b0),
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// Receive
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.gtwiz_userclk_rx_reset_in(1'b0),
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.gtwiz_userclk_rx_srcclk_out(),
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.gtwiz_userclk_rx_usrclk_out(),
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.gtwiz_userclk_rx_usrclk2_out(phy_rx_clk),
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.gtwiz_userclk_rx_active_out(),
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.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
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.gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath),
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.gtwiz_reset_rx_cdr_stable_out(),
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.gtwiz_reset_rx_done_out(gt_reset_rx_done),
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.rxpmaresetdone_out(),
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.rxprgdivresetdone_out(),
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.rxgearboxslip_in(gt_rxgearboxslip),
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.gtwiz_userdata_rx_out(gt_rxdata),
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.rxdatavalid_out(gt_rxdatavalid),
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.rxheader_out(gt_rxheader),
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.rxheadervalid_out(gt_rxheadervalid),
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.rxstartofseq_out()
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);
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assign xcvr_qpll0lock_out = 1'b0;
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assign xcvr_qpll0clk_out = 1'b0;
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assign xcvr_qpll0refclk_out = 1'b0;
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end
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endgenerate
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sync_reset #(
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.N(4)
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)
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tx_reset_sync_inst (
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.clk(phy_tx_clk),
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.rst(!gt_reset_tx_done),
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.out(phy_tx_rst)
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);
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sync_reset #(
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.N(4)
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)
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rx_reset_sync_inst (
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.clk(phy_rx_clk),
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.rst(!gt_reset_rx_done),
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.out(phy_rx_rst)
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);
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eth_phy_10g #(
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.DATA_WIDTH(DATA_WIDTH),
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.CTRL_WIDTH(CTRL_WIDTH),
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.HDR_WIDTH(HDR_WIDTH),
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.BIT_REVERSE(1),
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.SCRAMBLER_DISABLE(0),
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.PRBS31_ENABLE(PRBS31_ENABLE),
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.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
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.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
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.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
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.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
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.COUNT_125US(COUNT_125US)
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)
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phy_inst (
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.tx_clk(phy_tx_clk),
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.tx_rst(phy_tx_rst),
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.rx_clk(phy_rx_clk),
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.rx_rst(phy_rx_rst),
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.xgmii_txd(phy_xgmii_txd),
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.xgmii_txc(phy_xgmii_txc),
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.xgmii_rxd(phy_xgmii_rxd),
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.xgmii_rxc(phy_xgmii_rxc),
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.serdes_tx_data(gt_txdata),
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.serdes_tx_hdr(gt_txheader),
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.serdes_rx_data(gt_rxdata),
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.serdes_rx_hdr(gt_rxheader),
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.serdes_rx_bitslip(gt_rxgearboxslip),
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.serdes_rx_reset_req(phy_rx_reset_req),
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.tx_bad_block(phy_tx_bad_block),
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.rx_error_count(phy_rx_error_count),
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.rx_bad_block(phy_rx_bad_block),
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.rx_sequence_error(phy_rx_sequence_error),
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.rx_block_lock(phy_rx_block_lock),
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.rx_high_ber(phy_rx_high_ber),
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.rx_status(phy_rx_status),
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.cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable),
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.cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable)
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);
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endmodule
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`resetall
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