Alex Forencich 412df8fea0 Use unified 10G/25G design for fb2CG@KU15P
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-07-13 21:34:53 -07:00

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# Verilog Ethernet fb2CG@KU15P Example Design
## Introduction
This example design targets the Silicom fb2CG@KU15P FPGA board.
The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
will echo back any packets received. The design will also respond correctly
to ARP requests.
* FPGA: xcku15p-ffve1760-2-e
* PHY: 10G BASE-R PHY IP core and internal GTY transceiver
## How to build
Run make to build. Ensure that the Xilinx Vivado toolchain components are
in PATH.
## How to test
Run make program to program the fb2CG@KU15P board with Vivado. Then run
netcat -u 192.168.1.128 1234
to open a UDP connection to port 1234. Any text entered into netcat will be
echoed back after pressing enter.
It is also possible to use hping to test the design by running
hping 192.168.1.128 -2 -p 1234 -d 1024