FPGA/verilog-ethernet
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verilog-ethernet/rtl
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Alex Forencich baac5f8d81 Reorganize PTP timestamp capture logic; determine PTP clock step size from PTP time instead of parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2024-02-12 17:29:31 -08:00
..
arp_cache.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
arp_eth_rx.v
Use internal BYTE_LANES parameter
2023-07-06 16:28:08 -07:00
arp_eth_tx.v
Use internal BYTE_LANES parameter
2023-07-06 16:28:08 -07:00
arp.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
axis_baser_rx_64.v
Reorganize PTP timestamp capture logic; determine PTP clock step size from PTP time instead of parameters
2024-02-12 17:29:31 -08:00
axis_baser_tx_64.v
Reorganize PTP timestamp capture logic; determine PTP clock step size from PTP time instead of parameters
2024-02-12 17:29:31 -08:00
axis_eth_fcs_check_64.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
axis_eth_fcs_check.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
axis_eth_fcs_insert_64.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
axis_eth_fcs_insert.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
axis_eth_fcs.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
axis_gmii_rx.v
Add TX and RX enable inputs to MACs
2023-08-24 01:24:33 -07:00
axis_gmii_tx.v
Rework MAC TX error handling to streamline logic; pad errored frames to avoid generating runt frames
2024-01-29 18:33:14 -08:00
axis_xgmii_rx_32.v
Unconditionally transfer out XGMII data in XGMII RX modules
2024-01-28 14:43:59 -08:00
axis_xgmii_rx_64.v
Reorganize PTP timestamp capture logic; determine PTP clock step size from PTP time instead of parameters
2024-02-12 17:29:31 -08:00
axis_xgmii_tx_32.v
Rework MAC TX error handling to streamline logic; pad errored frames to avoid generating runt frames
2024-01-29 18:33:14 -08:00
axis_xgmii_tx_64.v
Reorganize PTP timestamp capture logic; determine PTP clock step size from PTP time instead of parameters
2024-02-12 17:29:31 -08:00
eth_arb_mux.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
eth_axis_rx.v
Use internal BYTE_LANES parameter
2023-07-06 16:28:08 -07:00
eth_axis_tx.v
Use internal BYTE_LANES parameter
2023-07-06 16:28:08 -07:00
eth_demux.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
eth_mac_1g_fifo.v
Add TX and RX enable inputs to MACs
2023-08-24 01:24:33 -07:00
eth_mac_1g_gmii_fifo.v
Add TX and RX enable inputs to MACs
2023-08-24 01:24:33 -07:00
eth_mac_1g_gmii.v
Add TX and RX enable inputs to MACs
2023-08-24 01:24:33 -07:00
eth_mac_1g_rgmii_fifo.v
Add TX and RX enable inputs to MACs
2023-08-24 01:24:33 -07:00
eth_mac_1g_rgmii.v
Add TX and RX enable inputs to MACs
2023-08-24 01:24:33 -07:00
eth_mac_1g.v
Clean up PTP parameters on MACs
2024-02-11 13:00:37 -08:00
eth_mac_10g_fifo.v
Reorganize PTP timestamp capture logic; determine PTP clock step size from PTP time instead of parameters
2024-02-12 17:29:31 -08:00
eth_mac_10g.v
Reorganize PTP timestamp capture logic; determine PTP clock step size from PTP time instead of parameters
2024-02-12 17:29:31 -08:00
eth_mac_mii_fifo.v
Add TX and RX enable inputs to MACs
2023-08-24 01:24:33 -07:00
eth_mac_mii.v
Add TX and RX enable inputs to MACs
2023-08-24 01:24:33 -07:00
eth_mac_phy_10g_fifo.v
Reorganize PTP timestamp capture logic; determine PTP clock step size from PTP time instead of parameters
2024-02-12 17:29:31 -08:00
eth_mac_phy_10g_rx.v
Reorganize PTP timestamp capture logic; determine PTP clock step size from PTP time instead of parameters
2024-02-12 17:29:31 -08:00
eth_mac_phy_10g_tx.v
Reorganize PTP timestamp capture logic; determine PTP clock step size from PTP time instead of parameters
2024-02-12 17:29:31 -08:00
eth_mac_phy_10g.v
Reorganize PTP timestamp capture logic; determine PTP clock step size from PTP time instead of parameters
2024-02-12 17:29:31 -08:00
eth_mux.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
eth_phy_10g_rx_ber_mon.v
Force possible floating point parameter value to integer when taking clog2
2022-11-01 23:56:27 -07:00
eth_phy_10g_rx_frame_sync.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
eth_phy_10g_rx_if.v
Add register on PRBS checker output in 10G PHY RX to improve timing performance
2024-01-14 16:10:20 -08:00
eth_phy_10g_rx_watchdog.v
Force possible floating point parameter value to integer when taking clog2
2022-11-01 23:56:27 -07:00
eth_phy_10g_rx.v
Use cfg prefix for configuration signals
2023-08-22 17:14:52 -07:00
eth_phy_10g_tx_if.v
Use cfg prefix for configuration signals
2023-08-22 17:14:52 -07:00
eth_phy_10g_tx.v
Use cfg prefix for configuration signals
2023-08-22 17:14:52 -07:00
eth_phy_10g.v
Use cfg prefix for configuration signals
2023-08-22 17:14:52 -07:00
gmii_phy_if.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
iddr.v
Fix timing of IDDR2 on Spartan 6
2023-01-01 21:44:15 -08:00
ip_64.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ip_arb_mux.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
ip_complete_64.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ip_complete.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ip_demux.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
ip_eth_rx_64.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
ip_eth_rx.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
ip_eth_tx_64.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
ip_eth_tx.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
ip_mux.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
ip.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
lfsr.v
Update lfsr.v
2023-01-15 12:36:03 -08:00
mac_ctrl_rx.v
Add MAC control layer modules
2023-07-22 00:47:15 -07:00
mac_ctrl_tx.v
Add MAC control layer modules
2023-07-22 00:47:15 -07:00
mac_pause_ctrl_rx.v
Add pause/PFC modules
2023-07-23 16:31:33 -07:00
mac_pause_ctrl_tx.v
Add pause/PFC modules
2023-07-23 16:31:33 -07:00
mii_phy_if.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
oddr.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ptp_clock_cdc.v
Rewrite gain scheduling
2023-12-01 22:02:40 -08:00
ptp_clock.v
Remove unnecessary resets
2023-11-01 18:30:32 -07:00
ptp_perout.v
More extensive overhaul of the PTP period output module to improve resource consumption and parallelize computation
2024-01-16 17:01:03 -08:00
ptp_tag_insert.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ptp_td_leaf.v
Split out and pipeline relative timestamp LSB increment in PTP TD leaf clock
2024-02-05 16:22:02 -08:00
ptp_td_phc.v
Move alternate offset switch near the end of the current second to extend reconstruction range for timestamps in the past
2024-02-11 13:01:03 -08:00
ptp_td_rel2tod.v
Add ptp_td_rel2tod module for timestamp reconstruction
2024-02-11 13:01:29 -08:00
ptp_ts_extract.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
rgmii_phy_if.v
Cleanup RGMII PHY IF, fix TX error indication
2024-01-29 16:10:58 -08:00
ssio_ddr_in_diff.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ssio_ddr_in.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ssio_ddr_out_diff.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ssio_ddr_out.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ssio_sdr_in_diff.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ssio_sdr_in.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ssio_sdr_out_diff.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ssio_sdr_out.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
udp_64.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
udp_arb_mux.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
udp_checksum_gen_64.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
udp_checksum_gen.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
udp_complete_64.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
udp_complete.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
udp_demux.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
udp_ip_rx_64.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
udp_ip_rx.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
udp_ip_tx_64.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
udp_ip_tx.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
udp_mux.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
udp.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
xgmii_baser_dec_64.v
Optimize block type decoding in 10G PHY RX to reduce fanin
2024-01-14 16:14:57 -08:00
xgmii_baser_enc_64.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
xgmii_deinterleave.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
xgmii_interleave.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00