mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
645 lines
21 KiB
Verilog
645 lines
21 KiB
Verilog
/*
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Copyright (c) 2015-2023 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* 1G Ethernet MAC
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*/
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module eth_mac_1g #
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(
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parameter DATA_WIDTH = 8,
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parameter ENABLE_PADDING = 1,
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parameter MIN_FRAME_LENGTH = 64,
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parameter PTP_TS_ENABLE = 0,
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parameter PTP_TS_FMT_TOD = 1,
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parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64,
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parameter TX_PTP_TS_CTRL_IN_TUSER = 0,
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parameter TX_PTP_TAG_ENABLE = PTP_TS_ENABLE,
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parameter TX_PTP_TAG_WIDTH = 16,
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parameter TX_USER_WIDTH = (PTP_TS_ENABLE ? (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + (TX_PTP_TS_CTRL_IN_TUSER ? 1 : 0) : 0) + 1,
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parameter RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
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parameter PFC_ENABLE = 0,
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parameter PAUSE_ENABLE = PFC_ENABLE
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)
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(
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input wire rx_clk,
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input wire rx_rst,
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input wire tx_clk,
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input wire tx_rst,
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/*
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* AXI input
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*/
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input wire [DATA_WIDTH-1:0] tx_axis_tdata,
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input wire tx_axis_tvalid,
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output wire tx_axis_tready,
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input wire tx_axis_tlast,
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input wire [TX_USER_WIDTH-1:0] tx_axis_tuser,
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/*
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* AXI output
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*/
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output wire [DATA_WIDTH-1:0] rx_axis_tdata,
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output wire rx_axis_tvalid,
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output wire rx_axis_tlast,
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output wire [RX_USER_WIDTH-1:0] rx_axis_tuser,
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/*
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* GMII interface
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*/
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input wire [DATA_WIDTH-1:0] gmii_rxd,
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input wire gmii_rx_dv,
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input wire gmii_rx_er,
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output wire [DATA_WIDTH-1:0] gmii_txd,
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output wire gmii_tx_en,
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output wire gmii_tx_er,
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/*
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* PTP
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*/
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input wire [PTP_TS_WIDTH-1:0] tx_ptp_ts,
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input wire [PTP_TS_WIDTH-1:0] rx_ptp_ts,
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output wire [PTP_TS_WIDTH-1:0] tx_axis_ptp_ts,
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output wire [TX_PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag,
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output wire tx_axis_ptp_ts_valid,
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/*
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* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
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*/
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input wire tx_lfc_req,
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input wire tx_lfc_resend,
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input wire rx_lfc_en,
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output wire rx_lfc_req,
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input wire rx_lfc_ack,
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/*
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* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
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*/
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input wire [7:0] tx_pfc_req,
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input wire tx_pfc_resend,
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input wire [7:0] rx_pfc_en,
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output wire [7:0] rx_pfc_req,
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input wire [7:0] rx_pfc_ack,
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/*
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* Pause interface
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*/
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input wire tx_lfc_pause_en,
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input wire tx_pause_req,
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output wire tx_pause_ack,
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/*
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* Control
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*/
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input wire rx_clk_enable,
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input wire tx_clk_enable,
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input wire rx_mii_select,
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input wire tx_mii_select,
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/*
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* Status
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*/
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output wire tx_start_packet,
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output wire tx_error_underflow,
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output wire rx_start_packet,
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output wire rx_error_bad_frame,
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output wire rx_error_bad_fcs,
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output wire stat_tx_mcf,
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output wire stat_rx_mcf,
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output wire stat_tx_lfc_pkt,
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output wire stat_tx_lfc_xon,
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output wire stat_tx_lfc_xoff,
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output wire stat_tx_lfc_paused,
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output wire stat_tx_pfc_pkt,
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output wire [7:0] stat_tx_pfc_xon,
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output wire [7:0] stat_tx_pfc_xoff,
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output wire [7:0] stat_tx_pfc_paused,
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output wire stat_rx_lfc_pkt,
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output wire stat_rx_lfc_xon,
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output wire stat_rx_lfc_xoff,
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output wire stat_rx_lfc_paused,
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output wire stat_rx_pfc_pkt,
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output wire [7:0] stat_rx_pfc_xon,
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output wire [7:0] stat_rx_pfc_xoff,
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output wire [7:0] stat_rx_pfc_paused,
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/*
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* Configuration
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*/
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input wire [7:0] cfg_ifg,
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input wire cfg_tx_enable,
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input wire cfg_rx_enable,
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input wire [47:0] cfg_mcf_rx_eth_dst_mcast,
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input wire cfg_mcf_rx_check_eth_dst_mcast,
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input wire [47:0] cfg_mcf_rx_eth_dst_ucast,
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input wire cfg_mcf_rx_check_eth_dst_ucast,
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input wire [47:0] cfg_mcf_rx_eth_src,
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input wire cfg_mcf_rx_check_eth_src,
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input wire [15:0] cfg_mcf_rx_eth_type,
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input wire [15:0] cfg_mcf_rx_opcode_lfc,
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input wire cfg_mcf_rx_check_opcode_lfc,
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input wire [15:0] cfg_mcf_rx_opcode_pfc,
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input wire cfg_mcf_rx_check_opcode_pfc,
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input wire cfg_mcf_rx_forward,
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input wire cfg_mcf_rx_enable,
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input wire [47:0] cfg_tx_lfc_eth_dst,
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input wire [47:0] cfg_tx_lfc_eth_src,
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input wire [15:0] cfg_tx_lfc_eth_type,
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input wire [15:0] cfg_tx_lfc_opcode,
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input wire cfg_tx_lfc_en,
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input wire [15:0] cfg_tx_lfc_quanta,
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input wire [15:0] cfg_tx_lfc_refresh,
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input wire [47:0] cfg_tx_pfc_eth_dst,
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input wire [47:0] cfg_tx_pfc_eth_src,
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input wire [15:0] cfg_tx_pfc_eth_type,
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input wire [15:0] cfg_tx_pfc_opcode,
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input wire cfg_tx_pfc_en,
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input wire [8*16-1:0] cfg_tx_pfc_quanta,
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input wire [8*16-1:0] cfg_tx_pfc_refresh,
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input wire [15:0] cfg_rx_lfc_opcode,
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input wire cfg_rx_lfc_en,
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input wire [15:0] cfg_rx_pfc_opcode,
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input wire cfg_rx_pfc_en
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);
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parameter MAC_CTRL_ENABLE = PAUSE_ENABLE || PFC_ENABLE;
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parameter TX_USER_WIDTH_INT = MAC_CTRL_ENABLE ? (PTP_TS_ENABLE ? (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1 : 0) + 1 : TX_USER_WIDTH;
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wire [DATA_WIDTH-1:0] tx_axis_tdata_int;
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wire tx_axis_tvalid_int;
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wire tx_axis_tready_int;
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wire tx_axis_tlast_int;
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wire [TX_USER_WIDTH_INT-1:0] tx_axis_tuser_int;
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wire [DATA_WIDTH-1:0] rx_axis_tdata_int;
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wire rx_axis_tvalid_int;
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wire rx_axis_tlast_int;
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wire [RX_USER_WIDTH-1:0] rx_axis_tuser_int;
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axis_gmii_rx #(
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.DATA_WIDTH(DATA_WIDTH),
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.PTP_TS_ENABLE(PTP_TS_ENABLE),
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.PTP_TS_WIDTH(PTP_TS_WIDTH),
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.USER_WIDTH(RX_USER_WIDTH)
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)
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axis_gmii_rx_inst (
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.clk(rx_clk),
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.rst(rx_rst),
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.gmii_rxd(gmii_rxd),
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.gmii_rx_dv(gmii_rx_dv),
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.gmii_rx_er(gmii_rx_er),
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.m_axis_tdata(rx_axis_tdata_int),
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.m_axis_tvalid(rx_axis_tvalid_int),
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.m_axis_tlast(rx_axis_tlast_int),
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.m_axis_tuser(rx_axis_tuser_int),
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.ptp_ts(rx_ptp_ts),
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.clk_enable(rx_clk_enable),
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.mii_select(rx_mii_select),
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.cfg_rx_enable(cfg_rx_enable),
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.start_packet(rx_start_packet),
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.error_bad_frame(rx_error_bad_frame),
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.error_bad_fcs(rx_error_bad_fcs)
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);
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axis_gmii_tx #(
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.DATA_WIDTH(DATA_WIDTH),
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.ENABLE_PADDING(ENABLE_PADDING),
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.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
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.PTP_TS_ENABLE(PTP_TS_ENABLE),
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.PTP_TS_WIDTH(PTP_TS_WIDTH),
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.PTP_TS_CTRL_IN_TUSER(MAC_CTRL_ENABLE ? PTP_TS_ENABLE : TX_PTP_TS_CTRL_IN_TUSER),
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.PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
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.PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH),
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.USER_WIDTH(TX_USER_WIDTH_INT)
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)
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axis_gmii_tx_inst (
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.clk(tx_clk),
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.rst(tx_rst),
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.s_axis_tdata(tx_axis_tdata_int),
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.s_axis_tvalid(tx_axis_tvalid_int),
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.s_axis_tready(tx_axis_tready_int),
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.s_axis_tlast(tx_axis_tlast_int),
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.s_axis_tuser(tx_axis_tuser_int),
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.gmii_txd(gmii_txd),
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.gmii_tx_en(gmii_tx_en),
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.gmii_tx_er(gmii_tx_er),
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.ptp_ts(tx_ptp_ts),
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.m_axis_ptp_ts(tx_axis_ptp_ts),
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.m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
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.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
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.clk_enable(tx_clk_enable),
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.mii_select(tx_mii_select),
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.cfg_ifg(cfg_ifg),
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.cfg_tx_enable(cfg_tx_enable),
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.start_packet(tx_start_packet),
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.error_underflow(tx_error_underflow)
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);
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generate
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if (MAC_CTRL_ENABLE) begin : mac_ctrl
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localparam MCF_PARAMS_SIZE = PFC_ENABLE ? 18 : 2;
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wire tx_mcf_valid;
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wire tx_mcf_ready;
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wire [47:0] tx_mcf_eth_dst;
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wire [47:0] tx_mcf_eth_src;
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wire [15:0] tx_mcf_eth_type;
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wire [15:0] tx_mcf_opcode;
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wire [MCF_PARAMS_SIZE*8-1:0] tx_mcf_params;
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wire rx_mcf_valid;
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wire [47:0] rx_mcf_eth_dst;
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wire [47:0] rx_mcf_eth_src;
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wire [15:0] rx_mcf_eth_type;
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wire [15:0] rx_mcf_opcode;
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wire [MCF_PARAMS_SIZE*8-1:0] rx_mcf_params;
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// terminate LFC pause requests from RX internally on TX side
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wire tx_pause_req_int;
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wire rx_lfc_ack_int;
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reg tx_lfc_req_sync_reg_1 = 1'b0;
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reg tx_lfc_req_sync_reg_2 = 1'b0;
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reg tx_lfc_req_sync_reg_3 = 1'b0;
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always @(posedge rx_clk or posedge rx_rst) begin
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if (rx_rst) begin
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tx_lfc_req_sync_reg_1 <= 1'b0;
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end else begin
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tx_lfc_req_sync_reg_1 <= rx_lfc_req;
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end
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end
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always @(posedge tx_clk or posedge tx_rst) begin
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if (tx_rst) begin
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tx_lfc_req_sync_reg_2 <= 1'b0;
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tx_lfc_req_sync_reg_3 <= 1'b0;
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end else begin
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tx_lfc_req_sync_reg_2 <= tx_lfc_req_sync_reg_1;
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tx_lfc_req_sync_reg_3 <= tx_lfc_req_sync_reg_2;
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end
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end
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reg rx_lfc_ack_sync_reg_1 = 1'b0;
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reg rx_lfc_ack_sync_reg_2 = 1'b0;
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reg rx_lfc_ack_sync_reg_3 = 1'b0;
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always @(posedge tx_clk or posedge tx_rst) begin
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if (tx_rst) begin
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rx_lfc_ack_sync_reg_1 <= 1'b0;
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end else begin
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rx_lfc_ack_sync_reg_1 <= tx_lfc_pause_en ? tx_pause_ack : 0;
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end
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end
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always @(posedge rx_clk or posedge rx_rst) begin
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if (rx_rst) begin
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rx_lfc_ack_sync_reg_2 <= 1'b0;
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rx_lfc_ack_sync_reg_3 <= 1'b0;
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end else begin
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rx_lfc_ack_sync_reg_2 <= rx_lfc_ack_sync_reg_1;
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rx_lfc_ack_sync_reg_3 <= rx_lfc_ack_sync_reg_2;
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end
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end
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assign tx_pause_req_int = tx_pause_req || (tx_lfc_pause_en ? tx_lfc_req_sync_reg_3 : 0);
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assign rx_lfc_ack_int = rx_lfc_ack || rx_lfc_ack_sync_reg_3;
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// handle PTP TS enable bit in tuser
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wire [TX_USER_WIDTH_INT-1:0] tx_axis_tuser_in;
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if (PTP_TS_ENABLE && !TX_PTP_TS_CTRL_IN_TUSER) begin
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assign tx_axis_tuser_in = {tx_axis_tuser[TX_USER_WIDTH-1:1], 1'b1, tx_axis_tuser[0]};
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end else begin
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assign tx_axis_tuser_in = tx_axis_tuser;
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end
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mac_ctrl_tx #(
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.DATA_WIDTH(DATA_WIDTH),
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.KEEP_ENABLE(0),
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.ID_ENABLE(0),
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.DEST_ENABLE(0),
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.USER_ENABLE(1),
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.USER_WIDTH(TX_USER_WIDTH_INT),
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.MCF_PARAMS_SIZE(MCF_PARAMS_SIZE)
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)
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mac_ctrl_tx_inst (
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.clk(tx_clk),
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.rst(tx_rst),
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/*
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* AXI stream input
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*/
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.s_axis_tdata(tx_axis_tdata),
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.s_axis_tkeep(1'b1),
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.s_axis_tvalid(tx_axis_tvalid),
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.s_axis_tready(tx_axis_tready),
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.s_axis_tlast(tx_axis_tlast),
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.s_axis_tid(0),
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.s_axis_tdest(0),
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.s_axis_tuser(tx_axis_tuser_in),
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/*
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* AXI stream output
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*/
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.m_axis_tdata(tx_axis_tdata_int),
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.m_axis_tkeep(),
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.m_axis_tvalid(tx_axis_tvalid_int),
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.m_axis_tready(tx_axis_tready_int),
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.m_axis_tlast(tx_axis_tlast_int),
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.m_axis_tid(),
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.m_axis_tdest(),
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.m_axis_tuser(tx_axis_tuser_int),
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/*
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* MAC control frame interface
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*/
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.mcf_valid(tx_mcf_valid),
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.mcf_ready(tx_mcf_ready),
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.mcf_eth_dst(tx_mcf_eth_dst),
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.mcf_eth_src(tx_mcf_eth_src),
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.mcf_eth_type(tx_mcf_eth_type),
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.mcf_opcode(tx_mcf_opcode),
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.mcf_params(tx_mcf_params),
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.mcf_id(0),
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.mcf_dest(0),
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.mcf_user(0),
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/*
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* Pause interface
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*/
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.tx_pause_req(tx_pause_req_int),
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.tx_pause_ack(tx_pause_ack),
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/*
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* Status
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*/
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.stat_tx_mcf(stat_tx_mcf)
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);
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mac_ctrl_rx #(
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.DATA_WIDTH(DATA_WIDTH),
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.KEEP_ENABLE(0),
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.ID_ENABLE(0),
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.DEST_ENABLE(0),
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.USER_ENABLE(1),
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.USER_WIDTH(RX_USER_WIDTH),
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.USE_READY(0),
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.MCF_PARAMS_SIZE(MCF_PARAMS_SIZE)
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)
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mac_ctrl_rx_inst (
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.clk(rx_clk),
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.rst(rx_rst),
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/*
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* AXI stream input
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*/
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.s_axis_tdata(rx_axis_tdata_int),
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.s_axis_tkeep(1'b1),
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.s_axis_tvalid(rx_axis_tvalid_int),
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.s_axis_tready(),
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.s_axis_tlast(rx_axis_tlast_int),
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.s_axis_tid(0),
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.s_axis_tdest(0),
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.s_axis_tuser(rx_axis_tuser_int),
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/*
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* AXI stream output
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*/
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.m_axis_tdata(rx_axis_tdata),
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.m_axis_tkeep(),
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.m_axis_tvalid(rx_axis_tvalid),
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.m_axis_tready(1'b1),
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.m_axis_tlast(rx_axis_tlast),
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.m_axis_tid(),
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.m_axis_tdest(),
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.m_axis_tuser(rx_axis_tuser),
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/*
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* MAC control frame interface
|
|
*/
|
|
.mcf_valid(rx_mcf_valid),
|
|
.mcf_eth_dst(rx_mcf_eth_dst),
|
|
.mcf_eth_src(rx_mcf_eth_src),
|
|
.mcf_eth_type(rx_mcf_eth_type),
|
|
.mcf_opcode(rx_mcf_opcode),
|
|
.mcf_params(rx_mcf_params),
|
|
.mcf_id(),
|
|
.mcf_dest(),
|
|
.mcf_user(),
|
|
|
|
/*
|
|
* Configuration
|
|
*/
|
|
.cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast),
|
|
.cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast),
|
|
.cfg_mcf_rx_eth_dst_ucast(cfg_mcf_rx_eth_dst_ucast),
|
|
.cfg_mcf_rx_check_eth_dst_ucast(cfg_mcf_rx_check_eth_dst_ucast),
|
|
.cfg_mcf_rx_eth_src(cfg_mcf_rx_eth_src),
|
|
.cfg_mcf_rx_check_eth_src(cfg_mcf_rx_check_eth_src),
|
|
.cfg_mcf_rx_eth_type(cfg_mcf_rx_eth_type),
|
|
.cfg_mcf_rx_opcode_lfc(cfg_mcf_rx_opcode_lfc),
|
|
.cfg_mcf_rx_check_opcode_lfc(cfg_mcf_rx_check_opcode_lfc),
|
|
.cfg_mcf_rx_opcode_pfc(cfg_mcf_rx_opcode_pfc),
|
|
.cfg_mcf_rx_check_opcode_pfc(cfg_mcf_rx_check_opcode_pfc),
|
|
.cfg_mcf_rx_forward(cfg_mcf_rx_forward),
|
|
.cfg_mcf_rx_enable(cfg_mcf_rx_enable),
|
|
|
|
/*
|
|
* Status
|
|
*/
|
|
.stat_rx_mcf(stat_rx_mcf)
|
|
);
|
|
|
|
mac_pause_ctrl_tx #(
|
|
.MCF_PARAMS_SIZE(MCF_PARAMS_SIZE),
|
|
.PFC_ENABLE(PFC_ENABLE)
|
|
)
|
|
mac_pause_ctrl_tx_inst (
|
|
.clk(tx_clk),
|
|
.rst(tx_rst),
|
|
|
|
/*
|
|
* MAC control frame interface
|
|
*/
|
|
.mcf_valid(tx_mcf_valid),
|
|
.mcf_ready(tx_mcf_ready),
|
|
.mcf_eth_dst(tx_mcf_eth_dst),
|
|
.mcf_eth_src(tx_mcf_eth_src),
|
|
.mcf_eth_type(tx_mcf_eth_type),
|
|
.mcf_opcode(tx_mcf_opcode),
|
|
.mcf_params(tx_mcf_params),
|
|
|
|
/*
|
|
* Pause (IEEE 802.3 annex 31B)
|
|
*/
|
|
.tx_lfc_req(tx_lfc_req),
|
|
.tx_lfc_resend(tx_lfc_resend),
|
|
|
|
/*
|
|
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D)
|
|
*/
|
|
.tx_pfc_req(tx_pfc_req),
|
|
.tx_pfc_resend(tx_pfc_resend),
|
|
|
|
/*
|
|
* Configuration
|
|
*/
|
|
.cfg_tx_lfc_eth_dst(cfg_tx_lfc_eth_dst),
|
|
.cfg_tx_lfc_eth_src(cfg_tx_lfc_eth_src),
|
|
.cfg_tx_lfc_eth_type(cfg_tx_lfc_eth_type),
|
|
.cfg_tx_lfc_opcode(cfg_tx_lfc_opcode),
|
|
.cfg_tx_lfc_en(cfg_tx_lfc_en),
|
|
.cfg_tx_lfc_quanta(cfg_tx_lfc_quanta),
|
|
.cfg_tx_lfc_refresh(cfg_tx_lfc_refresh),
|
|
.cfg_tx_pfc_eth_dst(cfg_tx_pfc_eth_dst),
|
|
.cfg_tx_pfc_eth_src(cfg_tx_pfc_eth_src),
|
|
.cfg_tx_pfc_eth_type(cfg_tx_pfc_eth_type),
|
|
.cfg_tx_pfc_opcode(cfg_tx_pfc_opcode),
|
|
.cfg_tx_pfc_en(cfg_tx_pfc_en),
|
|
.cfg_tx_pfc_quanta(cfg_tx_pfc_quanta),
|
|
.cfg_tx_pfc_refresh(cfg_tx_pfc_refresh),
|
|
.cfg_quanta_step(tx_mii_select ? (4*256)/512 : (8*256)/512),
|
|
.cfg_quanta_clk_en(tx_clk_enable),
|
|
|
|
/*
|
|
* Status
|
|
*/
|
|
.stat_tx_lfc_pkt(stat_tx_lfc_pkt),
|
|
.stat_tx_lfc_xon(stat_tx_lfc_xon),
|
|
.stat_tx_lfc_xoff(stat_tx_lfc_xoff),
|
|
.stat_tx_lfc_paused(stat_tx_lfc_paused),
|
|
.stat_tx_pfc_pkt(stat_tx_pfc_pkt),
|
|
.stat_tx_pfc_xon(stat_tx_pfc_xon),
|
|
.stat_tx_pfc_xoff(stat_tx_pfc_xoff),
|
|
.stat_tx_pfc_paused(stat_tx_pfc_paused)
|
|
);
|
|
|
|
mac_pause_ctrl_rx #(
|
|
.MCF_PARAMS_SIZE(18),
|
|
.PFC_ENABLE(PFC_ENABLE)
|
|
)
|
|
mac_pause_ctrl_rx_inst (
|
|
.clk(rx_clk),
|
|
.rst(rx_rst),
|
|
|
|
/*
|
|
* MAC control frame interface
|
|
*/
|
|
.mcf_valid(rx_mcf_valid),
|
|
.mcf_eth_dst(rx_mcf_eth_dst),
|
|
.mcf_eth_src(rx_mcf_eth_src),
|
|
.mcf_eth_type(rx_mcf_eth_type),
|
|
.mcf_opcode(rx_mcf_opcode),
|
|
.mcf_params(rx_mcf_params),
|
|
|
|
/*
|
|
* Pause (IEEE 802.3 annex 31B)
|
|
*/
|
|
.rx_lfc_en(rx_lfc_en),
|
|
.rx_lfc_req(rx_lfc_req),
|
|
.rx_lfc_ack(rx_lfc_ack_int),
|
|
|
|
/*
|
|
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D)
|
|
*/
|
|
.rx_pfc_en(rx_pfc_en),
|
|
.rx_pfc_req(rx_pfc_req),
|
|
.rx_pfc_ack(rx_pfc_ack),
|
|
|
|
/*
|
|
* Configuration
|
|
*/
|
|
.cfg_rx_lfc_opcode(cfg_rx_lfc_opcode),
|
|
.cfg_rx_lfc_en(cfg_rx_lfc_en),
|
|
.cfg_rx_pfc_opcode(cfg_rx_pfc_opcode),
|
|
.cfg_rx_pfc_en(cfg_rx_pfc_en),
|
|
.cfg_quanta_step(rx_mii_select ? (4*256)/512 : (8*256)/512),
|
|
.cfg_quanta_clk_en(rx_clk_enable),
|
|
|
|
/*
|
|
* Status
|
|
*/
|
|
.stat_rx_lfc_pkt(stat_rx_lfc_pkt),
|
|
.stat_rx_lfc_xon(stat_rx_lfc_xon),
|
|
.stat_rx_lfc_xoff(stat_rx_lfc_xoff),
|
|
.stat_rx_lfc_paused(stat_rx_lfc_paused),
|
|
.stat_rx_pfc_pkt(stat_rx_pfc_pkt),
|
|
.stat_rx_pfc_xon(stat_rx_pfc_xon),
|
|
.stat_rx_pfc_xoff(stat_rx_pfc_xoff),
|
|
.stat_rx_pfc_paused(stat_rx_pfc_paused)
|
|
);
|
|
|
|
end else begin
|
|
|
|
assign tx_axis_tdata_int = tx_axis_tdata;
|
|
assign tx_axis_tvalid_int = tx_axis_tvalid;
|
|
assign tx_axis_tready = tx_axis_tready_int;
|
|
assign tx_axis_tlast_int = tx_axis_tlast;
|
|
assign tx_axis_tuser_int = tx_axis_tuser;
|
|
|
|
assign rx_axis_tdata = rx_axis_tdata_int;
|
|
assign rx_axis_tvalid = rx_axis_tvalid_int;
|
|
assign rx_axis_tlast = rx_axis_tlast_int;
|
|
assign rx_axis_tuser = rx_axis_tuser_int;
|
|
|
|
assign rx_lfc_req = 0;
|
|
assign rx_pfc_req = 0;
|
|
assign tx_pause_ack = 0;
|
|
|
|
assign stat_tx_mcf = 0;
|
|
assign stat_rx_mcf = 0;
|
|
assign stat_tx_lfc_pkt = 0;
|
|
assign stat_tx_lfc_xon = 0;
|
|
assign stat_tx_lfc_xoff = 0;
|
|
assign stat_tx_lfc_paused = 0;
|
|
assign stat_tx_pfc_pkt = 0;
|
|
assign stat_tx_pfc_xon = 0;
|
|
assign stat_tx_pfc_xoff = 0;
|
|
assign stat_tx_pfc_paused = 0;
|
|
assign stat_rx_lfc_pkt = 0;
|
|
assign stat_rx_lfc_xon = 0;
|
|
assign stat_rx_lfc_xoff = 0;
|
|
assign stat_rx_lfc_paused = 0;
|
|
assign stat_rx_pfc_pkt = 0;
|
|
assign stat_rx_pfc_xon = 0;
|
|
assign stat_rx_pfc_xoff = 0;
|
|
assign stat_rx_pfc_paused = 0;
|
|
|
|
end
|
|
|
|
endgenerate
|
|
|
|
endmodule
|
|
|
|
`resetall
|