mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
422 lines
15 KiB
Verilog
422 lines
15 KiB
Verilog
/*
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Copyright (c) 2023 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* MAC control transmit
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*/
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module mac_ctrl_tx #
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(
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parameter DATA_WIDTH = 8,
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parameter KEEP_ENABLE = DATA_WIDTH>8,
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parameter KEEP_WIDTH = DATA_WIDTH/8,
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parameter ID_ENABLE = 0,
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parameter ID_WIDTH = 8,
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parameter DEST_ENABLE = 0,
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parameter DEST_WIDTH = 8,
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parameter USER_ENABLE = 1,
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parameter USER_WIDTH = 1,
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parameter MCF_PARAMS_SIZE = 18
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI stream input
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*/
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input wire [DATA_WIDTH-1:0] s_axis_tdata,
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input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
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input wire s_axis_tvalid,
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output wire s_axis_tready,
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input wire s_axis_tlast,
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input wire [ID_WIDTH-1:0] s_axis_tid,
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input wire [DEST_WIDTH-1:0] s_axis_tdest,
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input wire [USER_WIDTH-1:0] s_axis_tuser,
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/*
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* AXI stream output
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*/
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output wire [DATA_WIDTH-1:0] m_axis_tdata,
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output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
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output wire m_axis_tvalid,
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input wire m_axis_tready,
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output wire m_axis_tlast,
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output wire [ID_WIDTH-1:0] m_axis_tid,
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output wire [DEST_WIDTH-1:0] m_axis_tdest,
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output wire [USER_WIDTH-1:0] m_axis_tuser,
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/*
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* MAC control frame interface
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*/
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input wire mcf_valid,
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output wire mcf_ready,
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input wire [47:0] mcf_eth_dst,
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input wire [47:0] mcf_eth_src,
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input wire [15:0] mcf_eth_type,
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input wire [15:0] mcf_opcode,
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input wire [MCF_PARAMS_SIZE*8-1:0] mcf_params,
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input wire [ID_WIDTH-1:0] mcf_id,
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input wire [DEST_WIDTH-1:0] mcf_dest,
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input wire [USER_WIDTH-1:0] mcf_user,
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/*
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* Pause interface
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*/
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input wire tx_pause_req,
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output wire tx_pause_ack,
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/*
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* Status
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*/
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output wire stat_tx_mcf
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);
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parameter BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1;
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parameter HDR_SIZE = 60;
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parameter CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES;
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parameter PTR_WIDTH = $clog2(CYCLE_COUNT);
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parameter OFFSET = HDR_SIZE % BYTE_LANES;
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// check configuration
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initial begin
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if (BYTE_LANES * 8 != DATA_WIDTH) begin
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$error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)");
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$finish;
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end
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if (MCF_PARAMS_SIZE > 44) begin
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$error("Error: Maximum MCF_PARAMS_SIZE is 44 bytes (instance %m)");
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$finish;
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end
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end
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/*
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MAC control frame
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Field Length
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Destination MAC address 6 octets [01:80:C2:00:00:01]
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Source MAC address 6 octets
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Ethertype 2 octets [0x8808]
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Opcode 2 octets
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Parameters 0-44 octets
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This module manages the transmission of MAC control frames. Control frames
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are accepted in parallel, serialized, and merged at a higher priority with
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data traffic.
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*/
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reg send_data_reg = 1'b0, send_data_next;
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reg send_mcf_reg = 1'b0, send_mcf_next;
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reg [PTR_WIDTH-1:0] ptr_reg = 0, ptr_next;
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reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
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reg mcf_ready_reg = 1'b0, mcf_ready_next;
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reg tx_pause_ack_reg = 1'b0, tx_pause_ack_next;
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reg stat_tx_mcf_reg = 1'b0, stat_tx_mcf_next;
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// internal datapath
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reg [DATA_WIDTH-1:0] m_axis_tdata_int;
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reg [KEEP_WIDTH-1:0] m_axis_tkeep_int;
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reg m_axis_tvalid_int;
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reg m_axis_tready_int_reg = 1'b0;
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reg m_axis_tlast_int;
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reg [ID_WIDTH-1:0] m_axis_tid_int;
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reg [DEST_WIDTH-1:0] m_axis_tdest_int;
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reg [USER_WIDTH-1:0] m_axis_tuser_int;
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wire m_axis_tready_int_early;
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assign s_axis_tready = s_axis_tready_reg;
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assign mcf_ready = mcf_ready_reg;
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assign tx_pause_ack = tx_pause_ack_reg;
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assign stat_tx_mcf = stat_tx_mcf_reg;
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integer k;
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always @* begin
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send_data_next = send_data_reg;
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send_mcf_next = send_mcf_reg;
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ptr_next = ptr_reg;
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s_axis_tready_next = 1'b0;
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mcf_ready_next = 1'b0;
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tx_pause_ack_next = tx_pause_ack_reg;
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stat_tx_mcf_next = 1'b0;
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m_axis_tdata_int = 0;
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m_axis_tkeep_int = 0;
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m_axis_tvalid_int = 1'b0;
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m_axis_tlast_int = 1'b0;
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m_axis_tid_int = 0;
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m_axis_tdest_int = 0;
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m_axis_tuser_int = 0;
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if (!send_data_reg && !send_mcf_reg) begin
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m_axis_tdata_int = s_axis_tdata;
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m_axis_tkeep_int = s_axis_tkeep;
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m_axis_tvalid_int = 1'b0;
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m_axis_tlast_int = s_axis_tlast;
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m_axis_tid_int = s_axis_tid;
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m_axis_tdest_int = s_axis_tdest;
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m_axis_tuser_int = s_axis_tuser;
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s_axis_tready_next = m_axis_tready_int_early && !tx_pause_req;
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tx_pause_ack_next = tx_pause_req;
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if (s_axis_tvalid && s_axis_tready) begin
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s_axis_tready_next = m_axis_tready_int_early;
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tx_pause_ack_next = 1'b0;
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m_axis_tvalid_int = 1'b1;
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if (s_axis_tlast) begin
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s_axis_tready_next = m_axis_tready_int_early && !mcf_valid && !mcf_ready;
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send_data_next = 1'b0;
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end else begin
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send_data_next = 1'b1;
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end
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end else if (mcf_valid) begin
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s_axis_tready_next = 1'b0;
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ptr_next = 0;
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send_mcf_next = 1'b1;
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mcf_ready_next = (CYCLE_COUNT == 1) && m_axis_tready_int_early;
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end
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end
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if (send_data_reg) begin
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m_axis_tdata_int = s_axis_tdata;
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m_axis_tkeep_int = s_axis_tkeep;
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m_axis_tvalid_int = 1'b0;
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m_axis_tlast_int = s_axis_tlast;
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m_axis_tid_int = s_axis_tid;
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m_axis_tdest_int = s_axis_tdest;
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m_axis_tuser_int = s_axis_tuser;
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s_axis_tready_next = m_axis_tready_int_early;
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if (s_axis_tvalid && s_axis_tready) begin
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m_axis_tvalid_int = 1'b1;
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if (s_axis_tlast) begin
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s_axis_tready_next = m_axis_tready_int_early && !tx_pause_req;
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send_data_next = 1'b0;
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if (mcf_valid) begin
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s_axis_tready_next = 1'b0;
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ptr_next = 0;
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send_mcf_next = 1'b1;
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mcf_ready_next = (CYCLE_COUNT == 1) && m_axis_tready_int_early;
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end
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end else begin
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send_data_next = 1'b1;
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end
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end
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end
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if (send_mcf_reg) begin
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mcf_ready_next = (CYCLE_COUNT == 1 || ptr_reg == CYCLE_COUNT-1) && m_axis_tready_int_early;
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if (m_axis_tready_int_reg) begin
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ptr_next = ptr_reg + 1;
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m_axis_tvalid_int = 1'b1;
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m_axis_tid_int = mcf_id;
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m_axis_tdest_int = mcf_dest;
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m_axis_tuser_int = mcf_user;
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`define _HEADER_FIELD_(offset, field) \
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if (ptr_reg == offset/BYTE_LANES) begin \
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m_axis_tdata_int[(offset%BYTE_LANES)*8 +: 8] = field; \
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m_axis_tkeep_int[offset%BYTE_LANES] = 1'b1; \
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end
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`_HEADER_FIELD_(0, mcf_eth_dst[5*8 +: 8])
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`_HEADER_FIELD_(1, mcf_eth_dst[4*8 +: 8])
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`_HEADER_FIELD_(2, mcf_eth_dst[3*8 +: 8])
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`_HEADER_FIELD_(3, mcf_eth_dst[2*8 +: 8])
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`_HEADER_FIELD_(4, mcf_eth_dst[1*8 +: 8])
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`_HEADER_FIELD_(5, mcf_eth_dst[0*8 +: 8])
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`_HEADER_FIELD_(6, mcf_eth_src[5*8 +: 8])
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`_HEADER_FIELD_(7, mcf_eth_src[4*8 +: 8])
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`_HEADER_FIELD_(8, mcf_eth_src[3*8 +: 8])
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`_HEADER_FIELD_(9, mcf_eth_src[2*8 +: 8])
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`_HEADER_FIELD_(10, mcf_eth_src[1*8 +: 8])
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`_HEADER_FIELD_(11, mcf_eth_src[0*8 +: 8])
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`_HEADER_FIELD_(12, mcf_eth_type[1*8 +: 8])
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`_HEADER_FIELD_(13, mcf_eth_type[0*8 +: 8])
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`_HEADER_FIELD_(14, mcf_opcode[1*8 +: 8])
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`_HEADER_FIELD_(15, mcf_opcode[0*8 +: 8])
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for (k = 0; k < HDR_SIZE-16; k = k + 1) begin
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if (ptr_reg == (16+k)/BYTE_LANES) begin
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if (k < MCF_PARAMS_SIZE) begin
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m_axis_tdata_int[((16+k)%BYTE_LANES)*8 +: 8] = mcf_params[k*8 +: 8];
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end else begin
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m_axis_tdata_int[((16+k)%BYTE_LANES)*8 +: 8] = 0;
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end
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m_axis_tkeep_int[(16+k)%BYTE_LANES] = 1'b1;
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end
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end
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if (ptr_reg == (HDR_SIZE-1)/BYTE_LANES) begin
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s_axis_tready_next = m_axis_tready_int_early && !tx_pause_req;
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mcf_ready_next = 1'b0;
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m_axis_tlast_int = 1'b1;
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send_mcf_next = 1'b0;
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stat_tx_mcf_next = 1'b1;
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end else begin
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mcf_ready_next = (ptr_next == CYCLE_COUNT-1) && m_axis_tready_int_early;
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end
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`undef _HEADER_FIELD_
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end
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end
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end
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always @(posedge clk) begin
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send_data_reg <= send_data_next;
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send_mcf_reg <= send_mcf_next;
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ptr_reg <= ptr_next;
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s_axis_tready_reg <= s_axis_tready_next;
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mcf_ready_reg <= mcf_ready_next;
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tx_pause_ack_reg <= tx_pause_ack_next;
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stat_tx_mcf_reg <= stat_tx_mcf_next;
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if (rst) begin
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send_data_reg <= 1'b0;
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send_mcf_reg <= 1'b0;
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ptr_reg <= 0;
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s_axis_tready_reg <= 1'b0;
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mcf_ready_reg <= 1'b0;
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tx_pause_ack_reg <= 1'b0;
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stat_tx_mcf_reg <= 1'b0;
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end
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end
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// output datapath logic
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reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
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reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
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reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
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reg m_axis_tlast_reg = 1'b0;
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reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
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reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
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reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
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reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
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reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
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reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
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reg temp_m_axis_tlast_reg = 1'b0;
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reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}};
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reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
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reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}};
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// datapath control
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reg store_axis_int_to_output;
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reg store_axis_int_to_temp;
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reg store_axis_temp_to_output;
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assign m_axis_tdata = m_axis_tdata_reg;
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assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
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assign m_axis_tvalid = m_axis_tvalid_reg;
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assign m_axis_tlast = m_axis_tlast_reg;
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assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
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assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
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assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
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always @* begin
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// transfer sink ready state to source
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m_axis_tvalid_next = m_axis_tvalid_reg;
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temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
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store_axis_int_to_output = 1'b0;
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store_axis_int_to_temp = 1'b0;
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store_axis_temp_to_output = 1'b0;
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if (m_axis_tready_int_reg) begin
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// input is ready
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if (m_axis_tready || !m_axis_tvalid_reg) begin
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// output is ready or currently not valid, transfer data to output
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m_axis_tvalid_next = m_axis_tvalid_int;
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store_axis_int_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_m_axis_tvalid_next = m_axis_tvalid_int;
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store_axis_int_to_temp = 1'b1;
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end
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end else if (m_axis_tready) begin
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// input is not ready, but output is ready
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m_axis_tvalid_next = temp_m_axis_tvalid_reg;
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temp_m_axis_tvalid_next = 1'b0;
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store_axis_temp_to_output = 1'b1;
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end
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end
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always @(posedge clk) begin
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m_axis_tvalid_reg <= m_axis_tvalid_next;
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m_axis_tready_int_reg <= m_axis_tready_int_early;
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temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
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// datapath
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if (store_axis_int_to_output) begin
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m_axis_tdata_reg <= m_axis_tdata_int;
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m_axis_tkeep_reg <= m_axis_tkeep_int;
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m_axis_tlast_reg <= m_axis_tlast_int;
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m_axis_tid_reg <= m_axis_tid_int;
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m_axis_tdest_reg <= m_axis_tdest_int;
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m_axis_tuser_reg <= m_axis_tuser_int;
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end else if (store_axis_temp_to_output) begin
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m_axis_tdata_reg <= temp_m_axis_tdata_reg;
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m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
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m_axis_tlast_reg <= temp_m_axis_tlast_reg;
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m_axis_tid_reg <= temp_m_axis_tid_reg;
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m_axis_tdest_reg <= temp_m_axis_tdest_reg;
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m_axis_tuser_reg <= temp_m_axis_tuser_reg;
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end
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if (store_axis_int_to_temp) begin
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temp_m_axis_tdata_reg <= m_axis_tdata_int;
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temp_m_axis_tkeep_reg <= m_axis_tkeep_int;
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temp_m_axis_tlast_reg <= m_axis_tlast_int;
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temp_m_axis_tid_reg <= m_axis_tid_int;
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temp_m_axis_tdest_reg <= m_axis_tdest_int;
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temp_m_axis_tuser_reg <= m_axis_tuser_int;
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end
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if (rst) begin
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m_axis_tvalid_reg <= 1'b0;
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m_axis_tready_int_reg <= 1'b0;
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temp_m_axis_tvalid_reg <= 1'b0;
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end
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end
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endmodule
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`resetall
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