mirror of
https://github.com/alexforencich/verilog-ethernet.git
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147 lines
3.9 KiB
Verilog
147 lines
3.9 KiB
Verilog
/*
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Copyright (c) 2015-2019 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ps / 1fs
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/*
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* Testbench for ptp_clock
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*/
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module test_ptp_clock;
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// Parameters
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parameter PERIOD_NS_WIDTH = 4;
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parameter OFFSET_NS_WIDTH = 4;
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parameter DRIFT_NS_WIDTH = 4;
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parameter FNS_WIDTH = 16;
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parameter PERIOD_NS = 4'h6;
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parameter PERIOD_FNS = 16'h6666;
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parameter DRIFT_ENABLE = 1;
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parameter DRIFT_NS = 4'h0;
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parameter DRIFT_FNS = 16'h0002;
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parameter DRIFT_RATE = 16'h0005;
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// Inputs
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reg clk = 0;
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reg rst = 0;
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reg [7:0] current_test = 0;
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reg [95:0] input_ts_96 = 0;
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reg input_ts_96_valid = 0;
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reg [63:0] input_ts_64 = 0;
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reg input_ts_64_valid = 0;
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reg [PERIOD_NS_WIDTH-1:0] input_period_ns = 0;
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reg [FNS_WIDTH-1:0] input_period_fns = 0;
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reg input_period_valid = 0;
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reg [OFFSET_NS_WIDTH-1:0] input_adj_ns = 0;
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reg [FNS_WIDTH-1:0] input_adj_fns = 0;
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reg [15:0] input_adj_count = 0;
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reg input_adj_valid = 0;
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reg [DRIFT_NS_WIDTH-1:0] input_drift_ns = 0;
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reg [FNS_WIDTH-1:0] input_drift_fns = 0;
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reg [15:0] input_drift_rate = 0;
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reg input_drift_valid = 0;
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// Outputs
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wire input_adj_active;
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wire [95:0] output_ts_96;
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wire [63:0] output_ts_64;
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wire output_ts_step;
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wire output_pps;
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initial begin
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// myhdl integration
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$from_myhdl(
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clk,
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rst,
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current_test,
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input_ts_96,
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input_ts_96_valid,
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input_ts_64,
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input_ts_64_valid,
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input_period_ns,
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input_period_fns,
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input_period_valid,
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input_adj_ns,
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input_adj_fns,
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input_adj_count,
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input_adj_valid,
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input_drift_ns,
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input_drift_fns,
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input_drift_rate,
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input_drift_valid
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);
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$to_myhdl(
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input_adj_active,
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output_ts_96,
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output_ts_64,
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output_ts_step,
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output_pps
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);
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// dump file
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$dumpfile("test_ptp_clock.lxt");
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$dumpvars(0, test_ptp_clock);
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end
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ptp_clock #(
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.PERIOD_NS_WIDTH(PERIOD_NS_WIDTH),
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.OFFSET_NS_WIDTH(OFFSET_NS_WIDTH),
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.DRIFT_NS_WIDTH (DRIFT_NS_WIDTH),
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.FNS_WIDTH(FNS_WIDTH),
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.PERIOD_NS(PERIOD_NS),
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.PERIOD_FNS(PERIOD_FNS),
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.DRIFT_ENABLE(DRIFT_ENABLE),
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.DRIFT_NS(DRIFT_NS),
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.DRIFT_FNS(DRIFT_FNS),
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.DRIFT_RATE(DRIFT_RATE)
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)
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UUT (
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.clk(clk),
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.rst(rst),
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.input_ts_96(input_ts_96),
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.input_ts_96_valid(input_ts_96_valid),
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.input_ts_64(input_ts_64),
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.input_ts_64_valid(input_ts_64_valid),
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.input_period_ns(input_period_ns),
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.input_period_fns(input_period_fns),
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.input_period_valid(input_period_valid),
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.input_adj_ns(input_adj_ns),
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.input_adj_fns(input_adj_fns),
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.input_adj_count(input_adj_count),
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.input_adj_valid(input_adj_valid),
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.input_adj_active(input_adj_active),
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.input_drift_ns(input_drift_ns),
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.input_drift_fns(input_drift_fns),
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.input_drift_rate(input_drift_rate),
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.input_drift_valid(input_drift_valid),
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.output_ts_96(output_ts_96),
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.output_ts_64(output_ts_64),
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.output_ts_step(output_ts_step),
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.output_pps(output_pps)
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);
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endmodule
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