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verilog-ethernet/example/ADM_PCIE_9V3/fpga_25g/fpga_10g
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Alex Forencich 5d61059488 Use quad wrappers in ADM-PCIE-9V3 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-08-26 00:36:39 -07:00
..
config.tcl
Use unified 10G/25G design for ADM-PCIE-9V3
2023-07-13 18:59:33 -07:00
Makefile
Use quad wrappers in ADM-PCIE-9V3 example design
2023-08-26 00:36:39 -07:00