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verilog-ethernet/example/AU50/fpga_25g/fpga
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Alex Forencich 72de6c653a Use quad wrappers in AU50 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-08-26 01:09:00 -07:00
..
config.tcl
Use unified 10G/25G design for Alveo U50
2023-07-13 20:40:38 -07:00
Makefile
Use quad wrappers in AU50 example design
2023-08-26 01:09:00 -07:00