mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
331 lines
8.3 KiB
Python
Executable File
331 lines
8.3 KiB
Python
Executable File
#!/usr/bin/env python
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"""
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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from myhdl import *
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import os
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import axis_ep
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import eth_ep
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import xgmii_ep
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import baser_serdes_ep
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module = 'eth_phy_10g_rx'
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testbench = 'test_%s_64' % module
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srcs = []
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srcs.append("../rtl/%s.v" % module)
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srcs.append("../rtl/eth_phy_10g_rx_if.v")
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srcs.append("../rtl/eth_phy_10g_rx_ber_mon.v")
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srcs.append("../rtl/eth_phy_10g_rx_frame_sync.v")
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srcs.append("../rtl/xgmii_baser_dec_64.v")
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srcs.append("../rtl/lfsr.v")
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srcs.append("%s.v" % testbench)
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src = ' '.join(srcs)
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build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
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def prbs31(width=8, state=0x7fffffff):
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while True:
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out = 0
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for i in range(width):
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if bool(state & 0x08000000) ^ bool(state & 0x40000000):
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state = ((state & 0x3fffffff) << 1) | 1
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out = out | 2**i
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else:
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state = (state & 0x3fffffff) << 1
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yield ~out & (2**width-1)
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def bench():
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# Parameters
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DATA_WIDTH = 64
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CTRL_WIDTH = (DATA_WIDTH/8)
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HDR_WIDTH = 2
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BIT_REVERSE = 0
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SCRAMBLER_DISABLE = 0
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PRBS31_ENABLE = 1
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SERDES_PIPELINE = 2
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SLIP_COUNT_WIDTH = 3
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COUNT_125US = 1250/6.4
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# Inputs
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clk = Signal(bool(0))
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rst = Signal(bool(0))
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current_test = Signal(intbv(0)[8:])
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serdes_rx_data = Signal(intbv(0)[DATA_WIDTH:])
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serdes_rx_hdr = Signal(intbv(1)[HDR_WIDTH:])
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rx_prbs31_enable = Signal(bool(0))
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serdes_rx_data_int = Signal(intbv(0)[DATA_WIDTH:])
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serdes_rx_hdr_int = Signal(intbv(1)[HDR_WIDTH:])
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# Outputs
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xgmii_rxd = Signal(intbv(0)[DATA_WIDTH:])
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xgmii_rxc = Signal(intbv(0)[CTRL_WIDTH:])
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serdes_rx_bitslip = Signal(bool(0))
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rx_error_count = Signal(intbv(0)[7:])
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rx_bad_block = Signal(bool(0))
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rx_block_lock = Signal(bool(0))
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rx_high_ber = Signal(bool(0))
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# sources and sinks
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source = baser_serdes_ep.BaseRSerdesSource()
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source_logic = source.create_logic(
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clk,
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tx_data=serdes_rx_data_int,
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tx_header=serdes_rx_hdr_int,
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name='source'
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)
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sink = xgmii_ep.XGMIISink()
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sink_logic = sink.create_logic(
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clk,
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rst,
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rxd=xgmii_rxd,
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rxc=xgmii_rxc,
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name='sink'
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)
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# DUT
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if os.system(build_cmd):
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raise Exception("Error running build command")
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dut = Cosimulation(
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"vvp -m myhdl %s.vvp -lxt2" % testbench,
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clk=clk,
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rst=rst,
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current_test=current_test,
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xgmii_rxd=xgmii_rxd,
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xgmii_rxc=xgmii_rxc,
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serdes_rx_data=serdes_rx_data,
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serdes_rx_hdr=serdes_rx_hdr,
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serdes_rx_bitslip=serdes_rx_bitslip,
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rx_error_count=rx_error_count,
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rx_bad_block=rx_bad_block,
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rx_block_lock=rx_block_lock,
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rx_high_ber=rx_high_ber,
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rx_prbs31_enable=rx_prbs31_enable
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)
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@always(delay(4))
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def clkgen():
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clk.next = not clk
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load_bit_offset = []
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prbs_en = Signal(bool(0))
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@instance
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def shift_bits():
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bit_offset = 0
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last_data = 0
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prbs_gen = prbs31(66)
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while True:
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yield clk.posedge
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if load_bit_offset:
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bit_offset = load_bit_offset.pop(0)
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if serdes_rx_bitslip:
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bit_offset += 1
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bit_offset = bit_offset % 66
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data = int(serdes_rx_data_int) << 2 | int(serdes_rx_hdr_int)
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out_data = ((last_data | data << 66) >> 66-bit_offset) & 0x3ffffffffffffffff
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last_data = data
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if prbs_en:
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out_data = next(prbs_gen)
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serdes_rx_data.next = out_data >> 2
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serdes_rx_hdr.next = out_data & 3
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@instance
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def check():
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yield delay(100)
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yield clk.posedge
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rst.next = 1
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yield clk.posedge
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rst.next = 0
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yield clk.posedge
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yield delay(100)
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yield clk.posedge
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# testbench stimulus
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# wait for block lock
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while not rx_block_lock:
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yield clk.posedge
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# dump garbage
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while not sink.empty():
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sink.recv()
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for payload_len in list(range(16,34)):
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yield clk.posedge
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print("test 1: test packet, length %d" % payload_len)
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current_test.next = 1
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test_frame = bytearray(range(payload_len))
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xgmii_frame = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame)
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source.send(xgmii_frame)
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yield sink.wait()
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rx_frame = sink.recv()
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assert rx_frame.data == xgmii_frame.data
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assert sink.empty()
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yield delay(100)
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yield clk.posedge
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print("test 2: back-to-back packets, length %d" % payload_len)
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current_test.next = 2
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test_frame1 = bytearray(range(payload_len))
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test_frame2 = bytearray(range(payload_len))
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xgmii_frame1 = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame1)
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xgmii_frame2 = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame2)
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source.send(xgmii_frame1)
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source.send(xgmii_frame2)
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yield sink.wait()
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rx_frame = sink.recv()
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assert rx_frame.data == xgmii_frame1.data
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yield sink.wait()
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rx_frame = sink.recv()
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assert rx_frame.data == xgmii_frame2.data
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assert sink.empty()
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yield delay(100)
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yield clk.posedge
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print("test 3: errored frame, length %d" % payload_len)
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current_test.next = 3
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test_frame1 = bytearray(range(payload_len))
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test_frame2 = bytearray(range(payload_len))
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xgmii_frame1 = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame1)
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xgmii_frame2 = xgmii_ep.XGMIIFrame(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame2)
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xgmii_frame1.error = 1
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source.send(xgmii_frame1)
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source.send(xgmii_frame2)
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yield sink.wait()
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rx_frame = sink.recv()
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#assert rx_frame.data == xgmii_frame1.data
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yield sink.wait()
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rx_frame = sink.recv()
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assert rx_frame.data == xgmii_frame2.data
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assert sink.empty()
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yield delay(100)
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yield clk.posedge
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print("test 4: test frame sync")
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current_test.next = 4
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assert rx_block_lock
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load_bit_offset.append(33)
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yield delay(600)
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assert not rx_block_lock
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assert rx_high_ber
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yield delay(3000)
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assert rx_block_lock
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yield delay(2000)
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assert not rx_high_ber
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yield delay(100)
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yield clk.posedge
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print("test 5: PRBS31 check")
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current_test.next = 5
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rx_prbs31_enable.next = True
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yield delay(100)
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for k in range(20):
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yield clk.posedge
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assert rx_error_count > 0
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prbs_en.next = True
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yield delay(100)
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for k in range(20):
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yield clk.posedge
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assert rx_error_count == 0
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prbs_en.next = False
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rx_prbs31_enable.next = False
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yield delay(100)
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raise StopSimulation
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return instances()
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def test_bench():
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sim = Simulation(bench())
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sim.run()
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if __name__ == '__main__':
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print("Running test...")
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test_bench()
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