FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00
Code Issues Projects Releases Wiki Activity
verilog-ethernet/tb/eth_mac_10g_fifo
History
Alex Forencich 060e55b915 Wait for correct PTP CDC instance to lock 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-09-18 16:39:30 -07:00
..
Makefile
Add TX PTP timestamp enable bit in tuser
2023-07-17 10:58:40 -07:00
test_eth_mac_10g_fifo.py
Wait for correct PTP CDC instance to lock
2023-09-18 16:39:30 -07:00