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verilog-ethernet
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verilog-ethernet
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example
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Arty
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fpga
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tb
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fpga_core
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Alex Forencich
079d6329cb
Migrate example design testbenches to cocotb
2020-12-28 01:11:03 -08:00
..
Makefile
Migrate example design testbenches to cocotb
2020-12-28 01:11:03 -08:00
test_fpga_core.py
Migrate example design testbenches to cocotb
2020-12-28 01:11:03 -08:00