FPGA/verilog-ethernet
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verilog-ethernet/rtl
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Alex Forencich 09a8fa51b6 Rename ports
2018-10-25 10:19:32 -07:00
..
arbiter.v
Happy new year
2018-02-26 12:25:20 -08:00
axis_adapter.v
Rename ports
2018-10-25 10:19:32 -07:00
axis_arb_mux.v
Use logical operators
2018-10-24 22:24:27 -07:00
axis_async_fifo.v
Merge axis_async_fifo and axis_async_frame_fifo, rename ports
2018-10-25 09:53:38 -07:00
axis_cobs_decode.v
Update FIFO instance, rename ports
2018-10-25 10:17:58 -07:00
axis_cobs_encode.v
Update FIFO instance, rename ports
2018-10-25 10:17:58 -07:00
axis_crosspoint.v
Convert generated crosspoint to verilog parametrized crosspoint
2018-10-24 13:44:39 -07:00
axis_demux.v
Convert generated demux to verilog parametrized demux
2018-10-24 22:16:05 -07:00
axis_fifo.v
Merge axis_fifo and axis_frame_fifo, rename ports
2018-10-24 23:16:06 -07:00
axis_frame_join.v
Convert generated frame joiner to verilog parametrized frame joiner
2018-10-24 17:07:22 -07:00
axis_frame_length_adjust_fifo.v
Update FIFO instance, rename ports
2018-10-25 10:15:16 -07:00
axis_frame_length_adjust.v
Update FIFO instance, rename ports
2018-10-25 10:15:16 -07:00
axis_ll_bridge.v
Happy new year
2018-02-26 12:25:20 -08:00
axis_mux.v
Use logical operators
2018-10-24 22:24:27 -07:00
axis_rate_limit.v
Happy new year
2018-02-26 12:25:20 -08:00
axis_register.v
Use logical operators
2018-10-24 22:24:27 -07:00
axis_srl_fifo.v
Happy new year
2018-02-26 12:25:20 -08:00
axis_srl_register.v
Happy new year
2018-02-26 12:25:20 -08:00
axis_stat_counter.v
Happy new year
2018-02-26 12:25:20 -08:00
axis_switch.v
Connect arbiter parameters to top level
2018-10-24 21:09:00 -07:00
axis_tap.v
Happy new year
2018-02-26 12:25:20 -08:00
ll_axis_bridge.v
Happy new year
2018-02-26 12:25:20 -08:00
priority_encoder.v
Happy new year
2018-02-26 12:25:20 -08:00