mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-02-04 07:13:13 +08:00
267 lines
7.7 KiB
Python
267 lines
7.7 KiB
Python
#!/usr/bin/env python
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"""
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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import itertools
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import logging
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import os
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import sys
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import cocotb_test.simulator
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge
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from cocotb.regression import TestFactory
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from cocotbext.eth import XgmiiSource, XgmiiSink, XgmiiFrame
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try:
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from baser import BaseRSerdesSource, BaseRSerdesSink
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except ImportError:
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# attempt import from current directory
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sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
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try:
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from baser import BaseRSerdesSource, BaseRSerdesSink
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finally:
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del sys.path[0]
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class TB:
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.start_soon(Clock(dut.tx_clk, 6.4, units="ns").start())
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cocotb.start_soon(Clock(dut.rx_clk, 6.4, units="ns").start())
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self.xgmii_source = XgmiiSource(dut.xgmii_txd, dut.xgmii_txc, dut.tx_clk, dut.tx_rst)
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self.xgmii_sink = XgmiiSink(dut.xgmii_rxd, dut.xgmii_rxc, dut.rx_clk, dut.rx_rst)
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self.serdes_source = BaseRSerdesSource(dut.serdes_rx_data, dut.serdes_rx_hdr, dut.rx_clk, slip=dut.serdes_rx_bitslip)
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self.serdes_sink = BaseRSerdesSink(dut.serdes_tx_data, dut.serdes_tx_hdr, dut.tx_clk)
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dut.cfg_tx_prbs31_enable.setimmediatevalue(0)
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dut.cfg_rx_prbs31_enable.setimmediatevalue(0)
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async def reset(self):
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self.dut.tx_rst.setimmediatevalue(0)
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self.dut.rx_rst.setimmediatevalue(0)
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await RisingEdge(self.dut.tx_clk)
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await RisingEdge(self.dut.tx_clk)
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self.dut.tx_rst.value = 1
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self.dut.rx_rst.value = 1
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await RisingEdge(self.dut.tx_clk)
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await RisingEdge(self.dut.tx_clk)
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self.dut.tx_rst.value = 0
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self.dut.rx_rst.value = 0
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await RisingEdge(self.dut.tx_clk)
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await RisingEdge(self.dut.tx_clk)
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async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
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tb = TB(dut)
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tb.xgmii_source.ifg = ifg
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tb.serdes_source.ifg = ifg
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await tb.reset()
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tb.log.info("Wait for block lock")
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while not dut.rx_block_lock.value.integer:
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await RisingEdge(dut.rx_clk)
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# clear out sink buffer
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tb.xgmii_sink.clear()
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test_frames = [payload_data(x) for x in payload_lengths()]
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for test_data in test_frames:
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test_frame = XgmiiFrame.from_payload(test_data)
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await tb.serdes_source.send(test_frame)
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for test_data in test_frames:
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rx_frame = await tb.xgmii_sink.recv()
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assert rx_frame.get_payload() == test_data
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assert rx_frame.check_fcs()
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assert tb.xgmii_sink.empty()
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await RisingEdge(dut.rx_clk)
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await RisingEdge(dut.rx_clk)
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async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
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tb = TB(dut)
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tb.xgmii_source.ifg = ifg
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tb.serdes_source.ifg = ifg
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await tb.reset()
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test_frames = [payload_data(x) for x in payload_lengths()]
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for test_data in test_frames:
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test_frame = XgmiiFrame.from_payload(test_data)
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await tb.xgmii_source.send(test_frame)
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for test_data in test_frames:
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rx_frame = await tb.serdes_sink.recv()
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assert rx_frame.get_payload() == test_data
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assert rx_frame.check_fcs()
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assert tb.serdes_sink.empty()
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await RisingEdge(dut.tx_clk)
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await RisingEdge(dut.tx_clk)
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async def run_test_rx_frame_sync(dut):
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tb = TB(dut)
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await tb.reset()
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tb.log.info("Wait for block lock")
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while not dut.rx_block_lock.value.integer:
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await RisingEdge(dut.rx_clk)
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assert dut.rx_block_lock.value.integer
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tb.log.info("Change offset")
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tb.serdes_source.bit_offset = 33
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for k in range(100):
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await RisingEdge(dut.rx_clk)
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tb.log.info("Check for lock lost")
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assert not dut.rx_block_lock.value.integer
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assert dut.rx_high_ber.value.integer
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for k in range(500):
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await RisingEdge(dut.rx_clk)
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tb.log.info("Check for block lock")
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assert dut.rx_block_lock.value.integer
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for k in range(300):
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await RisingEdge(dut.rx_clk)
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tb.log.info("Check for high BER deassert")
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assert not dut.rx_high_ber.value.integer
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await RisingEdge(dut.rx_clk)
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await RisingEdge(dut.rx_clk)
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def size_list():
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return list(range(60, 128)) + [512, 1514, 9214] + [60]*10
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def incrementing_payload(length):
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return bytearray(itertools.islice(itertools.cycle(range(256)), length))
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def cycle_en():
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return itertools.cycle([0, 0, 0, 1])
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if cocotb.SIM_NAME:
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for test in [run_test_rx, run_test_tx]:
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factory = TestFactory(test)
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factory.add_option("payload_lengths", [size_list])
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factory.add_option("payload_data", [incrementing_payload])
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factory.add_option("ifg", [12])
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factory.generate_tests()
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factory = TestFactory(run_test_rx_frame_sync)
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factory.generate_tests()
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# cocotb-test
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tests_dir = os.path.abspath(os.path.dirname(__file__))
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rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
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lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
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axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl'))
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def test_eth_phy_10g(request):
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dut = "eth_phy_10g"
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module = os.path.splitext(os.path.basename(__file__))[0]
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toplevel = dut
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verilog_sources = [
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os.path.join(rtl_dir, f"{dut}.v"),
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os.path.join(rtl_dir, f"{dut}_rx.v"),
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os.path.join(rtl_dir, f"{dut}_rx_if.v"),
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os.path.join(rtl_dir, f"{dut}_rx_ber_mon.v"),
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os.path.join(rtl_dir, f"{dut}_rx_frame_sync.v"),
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os.path.join(rtl_dir, f"{dut}_rx_watchdog.v"),
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os.path.join(rtl_dir, f"{dut}_tx.v"),
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os.path.join(rtl_dir, f"{dut}_tx_if.v"),
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os.path.join(rtl_dir, "xgmii_baser_dec_64.v"),
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os.path.join(rtl_dir, "xgmii_baser_enc_64.v"),
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os.path.join(rtl_dir, "lfsr.v"),
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]
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parameters = {}
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parameters['DATA_WIDTH'] = 64
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parameters['CTRL_WIDTH'] = parameters['DATA_WIDTH'] // 8
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parameters['HDR_WIDTH'] = 2
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parameters['BIT_REVERSE'] = 0
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parameters['SCRAMBLER_DISABLE'] = 0
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parameters['PRBS31_ENABLE'] = 1
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parameters['TX_SERDES_PIPELINE'] = 2
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parameters['RX_SERDES_PIPELINE'] = 2
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parameters['BITSLIP_HIGH_CYCLES'] = 1
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parameters['BITSLIP_LOW_CYCLES'] = 8
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parameters['COUNT_125US'] = int(1250/6.4)
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extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
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extra_env['COCOTB_RESOLVE_X'] = 'RANDOM'
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sim_build = os.path.join(tests_dir, "sim_build",
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request.node.name.replace('[', '-').replace(']', ''))
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cocotb_test.simulator.run(
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python_search=[tests_dir],
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verilog_sources=verilog_sources,
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toplevel=toplevel,
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module=module,
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parameters=parameters,
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sim_build=sim_build,
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extra_env=extra_env,
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)
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