FPGA/verilog-ethernet
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Alex Forencich 58201866f3 Add timing constraints
2019-03-28 17:53:51 -07:00
..
eth_mac_1g_gmii.tcl
Add timing constraints
2019-03-28 17:53:51 -07:00
eth_mac_1g_rgmii.tcl
Add timing constraints
2019-03-28 17:53:51 -07:00
eth_mac_fifo.tcl
Add timing constraints
2019-03-28 17:53:51 -07:00
gmii_phy_if.tcl
Add timing constraints
2019-03-28 17:53:51 -07:00
rgmii_phy_if.tcl
Add timing constraints
2019-03-28 17:53:51 -07:00