FPGA/verilog-ethernet
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verilog-ethernet/example/fb2CG/fpga_25g/fpga
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Alex Forencich c673ddbc14 Use quad wrappers in fb2CG@KU15P example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-08-26 00:37:44 -07:00
..
config.tcl
Use unified 10G/25G design for fb2CG@KU15P
2023-07-13 21:34:53 -07:00
Makefile
Use quad wrappers in fb2CG@KU15P example design
2023-08-26 00:37:44 -07:00