FPGA/verilog-ethernet
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verilog-ethernet/example/Arty/fpga/rtl
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Alex Forencich 0f2478d68c Fix wires
2021-10-20 17:21:16 -07:00
..
debounce_switch.v
Add Arty example design
2019-03-28 19:38:55 -07:00
fpga_core.v
Change default target parameter
2020-12-25 01:48:24 -08:00
fpga.v
Fix wires
2021-10-20 17:21:16 -07:00
sync_signal.v
Add Arty example design
2019-03-28 19:38:55 -07:00