FPGA/verilog-ethernet
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verilog-ethernet/example/ExaNIC_X10/fpga/rtl
History
Alex Forencich 0f2478d68c Fix wires
2021-10-20 17:21:16 -07:00
..
eth_xcvr_phy_wrapper.v
Rework GT instances in ExaNIC X10 design
2021-10-18 00:34:06 -07:00
fpga_core.v
Fix wires
2021-10-20 17:21:16 -07:00
fpga.v
Rework GT instances in ExaNIC X10 design
2021-10-18 00:34:06 -07:00
sync_signal.v
Add ExaNIC X10 example design
2019-01-08 17:22:01 -08:00