FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00
Code Issues Projects Releases Wiki Activity
verilog-ethernet/rtl
History
Alex Forencich 14a2caa994 Rework 10G ethernet MAC TX to add input register
2015-05-17 01:39:59 -07:00
..
arp_64.v
Ignore transient requests
2014-11-21 00:00:27 -08:00
arp_cache.v
Add ARP cache module
2014-11-20 22:54:08 -08:00
arp_eth_rx_64.v
Remove z from default states for FSM inference
2015-03-09 02:38:39 -07:00
arp_eth_rx.v
Remove z from default states for FSM inference
2015-03-09 02:38:39 -07:00
arp_eth_tx_64.v
Remove z from default states for FSM inference
2015-03-09 02:38:39 -07:00
arp_eth_tx.v
Remove z from default states for FSM inference
2015-03-09 02:38:39 -07:00
arp.v
Ignore transient requests
2014-11-21 00:00:27 -08:00
axis_eth_fcs_64.v
Add Ethernet FCS calculator modules
2015-02-26 16:11:04 -08:00
axis_eth_fcs_check_64.v
Write to _next instead of _reg in async block
2015-05-04 01:17:39 -07:00
axis_eth_fcs_check.v
Properly handle short packets
2015-03-04 13:06:29 -08:00
axis_eth_fcs_insert_64.v
Add 64-bit Ethernet FCS inserter
2015-03-04 00:33:26 -08:00
axis_eth_fcs_insert.v
Handle tlast on first cycle
2015-03-03 21:46:02 -08:00
axis_eth_fcs.v
Add Ethernet FCS calculator modules
2015-02-26 16:11:04 -08:00
eth_arb_mux_2.v
Add 2 port Ethernet mux components
2014-11-21 00:02:20 -08:00
eth_arb_mux_4.v
Reverse priority in arbitrated mux
2014-11-16 02:20:44 -08:00
eth_arb_mux_64_2.v
Add 2 port Ethernet mux components
2014-11-21 00:02:20 -08:00
eth_arb_mux_64_4.v
Reverse priority in arbitrated mux
2014-11-16 02:20:44 -08:00
eth_arb_mux_64.py
Reverse priority in arbitrated mux
2014-11-16 02:20:44 -08:00
eth_arb_mux.py
Reverse priority in arbitrated mux
2014-11-16 02:20:44 -08:00
eth_axis_rx_64.v
Remove z from default states for FSM inference
2015-03-09 02:38:39 -07:00
eth_axis_rx.v
Remove z from default states for FSM inference
2015-03-09 02:38:39 -07:00
eth_axis_tx_64.v
Remove z from default states for FSM inference
2015-03-09 02:38:39 -07:00
eth_axis_tx.v
Remove z from default states for FSM inference
2015-03-09 02:38:39 -07:00
eth_crc_8.v
Add Ethernet CRC modules
2015-02-25 14:40:26 -08:00
eth_crc_16.v
Add Ethernet CRC modules
2015-02-25 14:40:26 -08:00
eth_crc_24.v
Add Ethernet CRC modules
2015-02-25 14:40:26 -08:00
eth_crc_32.v
Add Ethernet CRC modules
2015-02-25 14:40:26 -08:00
eth_crc_40.v
Add Ethernet CRC modules
2015-02-25 14:40:26 -08:00
eth_crc_48.v
Add Ethernet CRC modules
2015-02-25 14:40:26 -08:00
eth_crc_56.v
Add Ethernet CRC modules
2015-02-25 14:40:26 -08:00
eth_crc_64.v
Add Ethernet CRC modules
2015-02-25 14:40:26 -08:00
eth_demux_4.v
Add ethernet demux module and testbench
2014-11-17 21:52:49 -08:00
eth_demux_64_4.v
Add ethernet demux module and testbench
2014-11-17 21:52:49 -08:00
eth_demux_64.py
Add ethernet demux module and testbench
2014-11-17 21:52:49 -08:00
eth_demux.py
Add ethernet demux module and testbench
2014-11-17 21:52:49 -08:00
eth_mac_1g_fifo.v
Feed through and synchronize FIFO status signals
2015-05-12 19:12:23 -07:00
eth_mac_1g_rx.v
Improve error signal handling
2015-05-07 19:08:16 -07:00
eth_mac_1g_tx.v
Add gigabit MAC module
2015-02-26 19:16:08 -08:00
eth_mac_1g.v
Add gigabit MAC module
2015-02-26 19:16:08 -08:00
eth_mac_10g_fifo.v
Feed through and synchronize FIFO status signals
2015-05-12 19:12:23 -07:00
eth_mac_10g_rx.v
Add default case
2015-05-16 22:34:29 -07:00
eth_mac_10g_tx.v
Rework 10G ethernet MAC TX to add input register
2015-05-17 01:39:59 -07:00
eth_mac_10g.v
Add 10G MAC module
2015-05-08 00:05:21 -07:00
eth_mux_2.v
Add 2 port Ethernet mux components
2014-11-21 00:02:20 -08:00
eth_mux_4.v
Rework header ready set
2014-11-17 19:27:45 -08:00
eth_mux_64_2.v
Add 2 port Ethernet mux components
2014-11-21 00:02:20 -08:00
eth_mux_64_4.v
Rework header ready set
2014-11-17 19:27:45 -08:00
eth_mux_64.py
Rework header ready set
2014-11-17 19:27:45 -08:00
eth_mux.py
Rework header ready set
2014-11-17 19:27:45 -08:00
gmii_phy_if.v
Put PHY interface registers into IOBs for timing
2015-02-28 18:24:20 -08:00
ip_64.v
Remove z from default states for FSM inference
2015-03-09 02:38:39 -07:00
ip_arb_mux_2.v
Add 2 port IP mux components
2015-02-26 22:05:07 -08:00
ip_arb_mux_4.v
Add IP arbitrated mux and testbench
2014-11-18 11:48:11 -08:00
ip_arb_mux_64_2.v
Add 2 port IP mux components
2015-02-26 22:05:07 -08:00
ip_arb_mux_64_4.v
Add IP arbitrated mux and testbench
2014-11-18 11:48:11 -08:00
ip_arb_mux_64.py
Add IP arbitrated mux and testbench
2014-11-18 11:48:11 -08:00
ip_arb_mux.py
Add IP arbitrated mux and testbench
2014-11-18 11:48:11 -08:00
ip_complete_64.v
Improve classifier logic by registering payload select signals
2015-02-28 19:14:22 -08:00
ip_complete.v
Improve classifier logic by registering payload select signals
2015-02-28 19:14:22 -08:00
ip_demux_4.v
Add IP demux and testbench
2014-11-18 12:36:12 -08:00
ip_demux_64_4.v
Add IP demux and testbench
2014-11-18 12:36:12 -08:00
ip_demux_64.py
Add IP demux and testbench
2014-11-18 12:36:12 -08:00
ip_demux.py
Add IP demux and testbench
2014-11-18 12:36:12 -08:00
ip_eth_rx_64.v
Improve ip_eth_rx_64 module timing performance
2015-05-08 21:06:33 -07:00
ip_eth_rx.v
Remove z from default states for FSM inference
2015-03-09 02:38:39 -07:00
ip_eth_tx_64.v
Fix frame_ptr_reg width
2015-05-12 16:57:14 -07:00
ip_eth_tx.v
Fix frame_ptr_reg width
2015-05-12 16:57:14 -07:00
ip_mux_2.v
Add 2 port IP mux components
2015-02-26 22:05:07 -08:00
ip_mux_4.v
Add IP mux module and testbench
2014-11-18 11:27:34 -08:00
ip_mux_64_2.v
Add 2 port IP mux components
2015-02-26 22:05:07 -08:00
ip_mux_64_4.v
Add IP mux module and testbench
2014-11-18 11:27:34 -08:00
ip_mux_64.py
Add IP mux module and testbench
2014-11-18 11:27:34 -08:00
ip_mux.py
Add IP mux module and testbench
2014-11-18 11:27:34 -08:00
ip.v
Remove z from default states for FSM inference
2015-03-09 02:38:39 -07:00
udp_64.v
Remove udp_ip_protocol input
2015-02-26 22:37:40 -08:00
udp_arb_mux_4.v
Add UDP arbitrated mux and testbench
2014-11-18 14:53:31 -08:00
udp_arb_mux_64_4.v
Add UDP arbitrated mux and testbench
2014-11-18 14:53:31 -08:00
udp_arb_mux_64.py
Add UDP arbitrated mux and testbench
2014-11-18 14:53:31 -08:00
udp_arb_mux.py
Add UDP arbitrated mux and testbench
2014-11-18 14:53:31 -08:00
udp_complete_64.v
Improve classifier logic by registering payload select signals
2015-02-28 19:14:22 -08:00
udp_complete.v
Improve classifier logic by registering payload select signals
2015-02-28 19:14:22 -08:00
udp_demux_4.v
Add UDP demux module and testbench
2014-11-18 15:17:50 -08:00
udp_demux_64_4.v
Add UDP demux module and testbench
2014-11-18 15:17:50 -08:00
udp_demux_64.py
Add UDP demux module and testbench
2014-11-18 15:17:50 -08:00
udp_demux.py
Add UDP demux module and testbench
2014-11-18 15:17:50 -08:00
udp_ip_rx_64.v
Remove z from default states for FSM inference
2015-03-09 02:38:39 -07:00
udp_ip_rx.v
Remove z from default states for FSM inference
2015-03-09 02:38:39 -07:00
udp_ip_tx_64.v
Remove z from default states for FSM inference
2015-03-09 02:38:39 -07:00
udp_ip_tx.v
Remove z from default states for FSM inference
2015-03-09 02:38:39 -07:00
udp_mux_4.v
Add UDP mux module and testbench
2014-11-18 14:41:48 -08:00
udp_mux_64_4.v
Add UDP mux module and testbench
2014-11-18 14:41:48 -08:00
udp_mux_64.py
Add UDP mux module and testbench
2014-11-18 14:41:48 -08:00
udp_mux.py
Add UDP mux module and testbench
2014-11-18 14:41:48 -08:00
udp.v
Remove udp_ip_protocol input
2015-02-26 22:37:40 -08:00