mirror of
https://github.com/alexforencich/verilog-ethernet.git
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73 lines
2.1 KiB
Makefile
73 lines
2.1 KiB
Makefile
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# FPGA settings
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FPGA_PART = xc6vlx130t-1ff1156
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FPGA_TOP = fpga
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FPGA_ARCH = spartan6
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# PROM settings
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#PROM = xc18v04
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#SPI_PROM_SIZE = (in bytes)
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# Files for synthesis
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SYN_FILES = rtl/fpga.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/debounce_switch.v
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SYN_FILES += rtl/sync_reset.v
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SYN_FILES += rtl/sync_signal.v
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SYN_FILES += lib/eth/rtl/iddr.v
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SYN_FILES += lib/eth/rtl/oddr.v
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SYN_FILES += lib/eth/rtl/ssio_sdr_in.v
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SYN_FILES += lib/eth/rtl/ssio_sdr_out.v
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SYN_FILES += lib/eth/rtl/gmii_phy_if.v
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SYN_FILES += lib/eth/rtl/eth_mac_1g_gmii_fifo.v
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SYN_FILES += lib/eth/rtl/eth_mac_1g_gmii.v
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SYN_FILES += lib/eth/rtl/eth_mac_1g.v
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SYN_FILES += lib/eth/rtl/axis_gmii_rx.v
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SYN_FILES += lib/eth/rtl/axis_gmii_tx.v
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SYN_FILES += lib/eth/rtl/lfsr.v
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SYN_FILES += lib/eth/rtl/eth_axis_rx.v
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SYN_FILES += lib/eth/rtl/eth_axis_tx.v
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SYN_FILES += lib/eth/rtl/udp_complete.v
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SYN_FILES += lib/eth/rtl/udp_checksum_gen.v
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SYN_FILES += lib/eth/rtl/udp.v
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SYN_FILES += lib/eth/rtl/udp_ip_rx.v
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SYN_FILES += lib/eth/rtl/udp_ip_tx.v
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SYN_FILES += lib/eth/rtl/ip_complete.v
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SYN_FILES += lib/eth/rtl/ip.v
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SYN_FILES += lib/eth/rtl/ip_eth_rx.v
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SYN_FILES += lib/eth/rtl/ip_eth_tx.v
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SYN_FILES += lib/eth/rtl/ip_arb_mux.v
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SYN_FILES += lib/eth/rtl/arp.v
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SYN_FILES += lib/eth/rtl/arp_cache.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx.v
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SYN_FILES += lib/eth/rtl/eth_arb_mux.v
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SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
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SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
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#SYN_FILES += coregen/dcm_i100_o125/dcm_i100_o125.v
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# UCF files
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UCF_FILES = fpga.ucf
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UCF_FILES += clock.ucf
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# NGC paths for ngdbuild
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#NGC_PATHS = coregen/dcm_i100_o125
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# Bitgen options
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BITGEN_OPTIONS = -g StartupClk:Cclk -g ConfigRate:26
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include ../common/xilinx.mk
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program: $(FPGA_TOP).bit
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echo "setmode -bscan" > program.cmd
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echo "setcable -p auto" >> program.cmd
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echo "identify" >> program.cmd
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echo "assignfile -p 2 -file $(FPGA_TOP).bit" >> program.cmd
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echo "program -p 2" >> program.cmd
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echo "quit" >> program.cmd
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impact -batch program.cmd
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