FPGA/verilog-ethernet
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verilog-ethernet/example/ML605/fpga_sgmii/common
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Alex Forencich cf6a01fffe Add ML605 SGMII design
2017-07-22 11:07:23 -07:00
..
xilinx.mk
Add ML605 SGMII design
2017-07-22 11:07:23 -07:00