FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-02-04 07:13:13 +08:00
Code Issues Projects Releases Wiki Activity
verilog-ethernet/example/VCU118/fpga_25g/tb
History
Alex Forencich 16e5ec2106 Update example designs
2019-07-18 17:13:47 -07:00
..
arp_ep.py
Add VCU118 25G example design
2019-06-19 23:25:06 -07:00
axis_ep.py
Add VCU118 25G example design
2019-06-19 23:25:06 -07:00
eth_ep.py
Add VCU118 25G example design
2019-06-19 23:25:06 -07:00
gmii_ep.py
Add VCU118 25G example design
2019-06-19 23:25:06 -07:00
ip_ep.py
Add VCU118 25G example design
2019-06-19 23:25:06 -07:00
test_fpga_core.py
Update example designs
2019-07-18 17:13:47 -07:00
test_fpga_core.v
Add VCU118 25G example design
2019-06-19 23:25:06 -07:00
udp_ep.py
Add VCU118 25G example design
2019-06-19 23:25:06 -07:00
xgmii_ep.py
Add VCU118 25G example design
2019-06-19 23:25:06 -07:00