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https://github.com/alexforencich/verilog-ethernet.git
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34 lines
584 B
Makefile
34 lines
584 B
Makefile
# Tools
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COREGEN:=coregen
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XAW2VERILOG:=xaw2verilog
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# Source
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XCO:=gig_eth_pcs_pma_v11_5.xco
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XAW:=
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# Targets
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TARGETS += $(XCO:.xco=)
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TARGETS += $(XAW:.xaw=)
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# Rules
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.PHONY: all
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all: $(TARGETS)
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.PHONY: clean
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clean:
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-rm -rf $(TARGETS)
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%: %.xco
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$(eval $@_TMP := $(shell mktemp -d))
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cp -a coregen.cgp $($@_TMP)
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cp -a $< $($@_TMP)
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cd $($@_TMP) && $(COREGEN) -p coregen.cgp -b $(notdir $<)
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mv $($@_TMP) $@
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%: %.xaw
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$(eval $@_TMP := $(shell mktemp -d))
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cp -a coregen.cgp $($@_TMP)
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cp -a $< $($@_TMP)
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cd $($@_TMP) && $(XAW2VERILOG) -st $(notdir $<) $(notdir $*)
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mv $($@_TMP) $@
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