FPGA/verilog-ethernet
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verilog-ethernet/example/Alveo/fpga_25g/rtl
History
Alex Forencich 1b29a88b18 Rename AU200 to Alveo 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-11-08 11:50:50 -08:00
..
debounce_switch.v
Rename AU200 to Alveo
2023-11-08 11:50:50 -08:00
eth_xcvr_phy_quad_wrapper.v
Rename AU200 to Alveo
2023-11-08 11:50:50 -08:00
eth_xcvr_phy_wrapper.v
Rename AU200 to Alveo
2023-11-08 11:50:50 -08:00
fpga_au200.v
Rename AU200 to Alveo
2023-11-08 11:50:50 -08:00
fpga_core.v
Rename AU200 to Alveo
2023-11-08 11:50:50 -08:00
sync_signal.v
Rename AU200 to Alveo
2023-11-08 11:50:50 -08:00