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verilog-ethernet/example/S10DX_DK
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Alex Forencich 1be196279f Fix FIFO instances in S10DX example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-07-17 11:05:24 -07:00
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fpga_10g
Fix FIFO instances in S10DX example design
2023-07-17 11:05:24 -07:00