mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
74 lines
4.3 KiB
Tcl
74 lines
4.3 KiB
Tcl
# XDC constraints for the Digilent Arty board
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# part: xc7a35t-csg324-1
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# General configuration
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
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# 100 MHz clock
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set_property -dict {LOC E3 IOSTANDARD LVCMOS33} [get_ports clk]
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create_clock -period 10.000 -name clk [get_ports clk]
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# LEDs
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set_property -dict {LOC G6 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led0_r]
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set_property -dict {LOC F6 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led0_g]
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set_property -dict {LOC E1 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led0_b]
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set_property -dict {LOC G3 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led1_r]
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set_property -dict {LOC J4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led1_g]
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set_property -dict {LOC G4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led1_b]
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set_property -dict {LOC J3 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led2_r]
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set_property -dict {LOC J2 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led2_g]
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set_property -dict {LOC H4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led2_b]
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set_property -dict {LOC K1 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led3_r]
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set_property -dict {LOC H6 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led3_g]
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set_property -dict {LOC K2 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led3_b]
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set_property -dict {LOC H5 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led4]
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set_property -dict {LOC J5 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led5]
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set_property -dict {LOC T9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led6]
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set_property -dict {LOC T10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led7]
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# Reset button
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set_property -dict {LOC C2 IOSTANDARD LVCMOS33} [get_ports reset_n]
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# Push buttons
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set_property -dict {LOC D9 IOSTANDARD LVCMOS33} [get_ports {btn[0]}]
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set_property -dict {LOC C9 IOSTANDARD LVCMOS33} [get_ports {btn[1]}]
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set_property -dict {LOC B9 IOSTANDARD LVCMOS33} [get_ports {btn[2]}]
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set_property -dict {LOC B8 IOSTANDARD LVCMOS33} [get_ports {btn[3]}]
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# Toggle switches
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set_property -dict {LOC A8 IOSTANDARD LVCMOS33} [get_ports {sw[0]}]
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set_property -dict {LOC C11 IOSTANDARD LVCMOS33} [get_ports {sw[1]}]
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set_property -dict {LOC C10 IOSTANDARD LVCMOS33} [get_ports {sw[2]}]
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set_property -dict {LOC A10 IOSTANDARD LVCMOS33} [get_ports {sw[3]}]
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# UART
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set_property -dict {LOC D10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports uart_txd]
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set_property -dict {LOC A9 IOSTANDARD LVCMOS33} [get_ports uart_rxd]
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# Ethernet MII PHY
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set_property -dict {LOC F15 IOSTANDARD LVCMOS33} [get_ports phy_rx_clk]
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set_property -dict {LOC D18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[0]}]
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set_property -dict {LOC E17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[1]}]
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set_property -dict {LOC E18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[2]}]
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set_property -dict {LOC G17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[3]}]
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set_property -dict {LOC G16 IOSTANDARD LVCMOS33} [get_ports phy_rx_dv]
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set_property -dict {LOC C17 IOSTANDARD LVCMOS33} [get_ports phy_rx_er]
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set_property -dict {LOC H16 IOSTANDARD LVCMOS33} [get_ports phy_tx_clk]
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set_property -dict {LOC H14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}]
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set_property -dict {LOC J14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}]
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set_property -dict {LOC J13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}]
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set_property -dict {LOC H17 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}]
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set_property -dict {LOC H15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports phy_tx_en]
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set_property -dict {LOC D17 IOSTANDARD LVCMOS33} [get_ports phy_col]
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set_property -dict {LOC G14 IOSTANDARD LVCMOS33} [get_ports phy_crs]
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set_property -dict {LOC G18 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_ref_clk]
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set_property -dict {LOC C16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_reset_n]
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#set_property -dict {LOC K13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_mdio]
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#set_property -dict {LOC F16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_mdc]
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create_clock -period 40.000 -name phy_rx_clk [get_ports phy_rx_clk]
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create_clock -period 40.000 -name phy_tx_clk [get_ports phy_tx_clk]
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