verilog-ethernet/axis_baser_rx_64 at 1f80696b55e84f807860aebd95b85e68631bcc10 - verilog-ethernet - Gitea: Git with a cup of tea

FPGA/verilog-ethernet

mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00

History

Alex Forencich 1f80696b55 Use start_soon instead of fork

2021-12-10 18:19:11 -08:00

..

baser.py

Add cocotb testbenches for AXI stream BASE-R TX and RX modules

2021-10-15 01:08:14 -07:00

Makefile

Add cocotb testbenches for AXI stream BASE-R TX and RX modules

2021-10-15 01:08:14 -07:00

test_axis_baser_rx_64.py

Use start_soon instead of fork

2021-12-10 18:19:11 -08:00