mirror of
https://github.com/alexforencich/verilog-ethernet.git
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740 lines
30 KiB
Verilog
740 lines
30 KiB
Verilog
/*
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Copyright (c) 2014 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* IP ethernet frame receiver (Ethernet frame in, IP frame out, 64 bit datapath)
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*/
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module ip_eth_rx_64
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(
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input wire clk,
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input wire rst,
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/*
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* Ethernet frame input
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*/
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input wire input_eth_hdr_valid,
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output wire input_eth_hdr_ready,
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input wire [47:0] input_eth_dest_mac,
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input wire [47:0] input_eth_src_mac,
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input wire [15:0] input_eth_type,
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input wire [63:0] input_eth_payload_tdata,
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input wire [7:0] input_eth_payload_tkeep,
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input wire input_eth_payload_tvalid,
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output wire input_eth_payload_tready,
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input wire input_eth_payload_tlast,
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input wire input_eth_payload_tuser,
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/*
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* IP frame output
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*/
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output wire output_ip_hdr_valid,
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input wire output_ip_hdr_ready,
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output wire [47:0] output_eth_dest_mac,
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output wire [47:0] output_eth_src_mac,
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output wire [15:0] output_eth_type,
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output wire [3:0] output_ip_version,
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output wire [3:0] output_ip_ihl,
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output wire [5:0] output_ip_dscp,
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output wire [1:0] output_ip_ecn,
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output wire [15:0] output_ip_length,
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output wire [15:0] output_ip_identification,
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output wire [2:0] output_ip_flags,
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output wire [12:0] output_ip_fragment_offset,
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output wire [7:0] output_ip_ttl,
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output wire [7:0] output_ip_protocol,
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output wire [15:0] output_ip_header_checksum,
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output wire [31:0] output_ip_source_ip,
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output wire [31:0] output_ip_dest_ip,
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output wire [63:0] output_ip_payload_tdata,
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output wire [7:0] output_ip_payload_tkeep,
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output wire output_ip_payload_tvalid,
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input wire output_ip_payload_tready,
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output wire output_ip_payload_tlast,
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output wire output_ip_payload_tuser,
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/*
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* Status signals
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*/
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output wire busy,
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output wire error_header_early_termination,
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output wire error_payload_early_termination,
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output wire error_invalid_header,
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output wire error_invalid_checksum
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);
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/*
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IP Frame
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Field Length
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Destination MAC address 6 octets
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Source MAC address 6 octets
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Ethertype (0x0800) 2 octets
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Version (4) 4 bits
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IHL (5-15) 4 bits
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DSCP (0) 6 bits
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ECN (0) 2 bits
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length 2 octets
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identification (0?) 2 octets
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flags (010) 3 bits
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fragment offset (0) 13 bits
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time to live (64?) 1 octet
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protocol 1 octet
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header checksum 2 octets
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source IP 4 octets
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destination IP 4 octets
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options (IHL-5)*4 octets
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payload length octets
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This module receives an Ethernet frame with decoded fields and decodes
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the AXI packet format. If the Ethertype does not match, the packet is
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discarded.
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*/
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localparam [3:0]
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STATE_IDLE = 4'd0,
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STATE_READ_HEADER = 4'd1,
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STATE_READ_PAYLOAD_IDLE = 4'd2,
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STATE_READ_PAYLOAD_TRANSFER = 4'd3,
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STATE_READ_PAYLOAD_TRANSFER_WAIT = 4'd4,
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STATE_READ_PAYLOAD_TRANSFER_LAST = 4'd5,
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STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST = 4'd6,
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STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST_WAIT = 4'd7,
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STATE_WAIT_LAST = 4'd8;
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reg [3:0] state_reg = STATE_IDLE, state_next;
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// datapath control signals
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reg store_eth_hdr;
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reg store_hdr_word_0;
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reg store_hdr_word_1;
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reg store_hdr_word_2;
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reg flush_save;
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reg transfer_in_save;
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reg transfer_save_out;
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reg transfer_in_out;
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reg transfer_in_temp;
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reg transfer_temp_out;
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reg assert_tlast;
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reg assert_tuser;
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reg [7:0] tkeep_mask;
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reg [15:0] frame_ptr_reg = 0, frame_ptr_next;
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reg [31:0] hdr_sum_temp;
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reg [15:0] hdr_sum_reg = 0, hdr_sum_next;
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reg [15:0] hdr_sum_temp_a_reg = 0, hdr_sum_temp_a_next;
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reg [15:0] hdr_sum_temp_b_reg = 0, hdr_sum_temp_b_next;
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reg input_eth_hdr_ready_reg = 0;
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reg input_eth_payload_tready_reg = 0;
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reg output_ip_hdr_valid_reg = 0, output_ip_hdr_valid_next;
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reg [47:0] output_eth_dest_mac_reg = 0;
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reg [47:0] output_eth_src_mac_reg = 0;
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reg [15:0] output_eth_type_reg = 0;
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reg [3:0] output_ip_version_reg = 0;
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reg [3:0] output_ip_ihl_reg = 0;
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reg [5:0] output_ip_dscp_reg = 0;
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reg [1:0] output_ip_ecn_reg = 0;
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reg [15:0] output_ip_length_reg = 0;
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reg [15:0] output_ip_identification_reg = 0;
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reg [2:0] output_ip_flags_reg = 0;
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reg [12:0] output_ip_fragment_offset_reg = 0;
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reg [7:0] output_ip_ttl_reg = 0;
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reg [7:0] output_ip_protocol_reg = 0;
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reg [15:0] output_ip_header_checksum_reg = 0;
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reg [31:0] output_ip_source_ip_reg = 0;
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reg [31:0] output_ip_dest_ip_reg = 0;
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reg [63:0] output_ip_payload_tdata_reg = 0;
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reg [7:0] output_ip_payload_tkeep_reg = 0;
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reg output_ip_payload_tvalid_reg = 0;
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reg output_ip_payload_tlast_reg = 0;
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reg output_ip_payload_tuser_reg = 0;
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reg busy_reg = 0;
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reg error_header_early_termination_reg = 0, error_header_early_termination_next;
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reg error_payload_early_termination_reg = 0, error_payload_early_termination_next;
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reg error_invalid_header_reg = 0, error_invalid_header_next;
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reg error_invalid_checksum_reg = 0, error_invalid_checksum_next;
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reg [63:0] temp_ip_payload_tdata_reg = 0;
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reg [7:0] temp_ip_payload_tkeep_reg = 0;
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reg temp_ip_payload_tlast_reg = 0;
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reg temp_ip_payload_tuser_reg = 0;
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reg [63:0] save_eth_payload_tdata_reg = 0;
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reg [7:0] save_eth_payload_tkeep_reg = 0;
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reg save_eth_payload_tlast_reg = 0;
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reg save_eth_payload_tuser_reg = 0;
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reg [63:0] shift_eth_payload_tdata;
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reg [7:0] shift_eth_payload_tkeep;
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reg shift_eth_payload_tvalid;
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reg shift_eth_payload_tlast;
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reg shift_eth_payload_tuser;
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reg shift_eth_payload_input_tready;
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reg shift_eth_payload_extra_cycle;
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assign input_eth_hdr_ready = input_eth_hdr_ready_reg;
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assign input_eth_payload_tready = input_eth_payload_tready_reg;
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assign output_ip_hdr_valid = output_ip_hdr_valid_reg;
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assign output_eth_dest_mac = output_eth_dest_mac_reg;
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assign output_eth_src_mac = output_eth_src_mac_reg;
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assign output_eth_type = output_eth_type_reg;
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assign output_ip_version = output_ip_version_reg;
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assign output_ip_ihl = output_ip_ihl_reg;
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assign output_ip_dscp = output_ip_dscp_reg;
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assign output_ip_ecn = output_ip_ecn_reg;
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assign output_ip_length = output_ip_length_reg;
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assign output_ip_identification = output_ip_identification_reg;
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assign output_ip_flags = output_ip_flags_reg;
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assign output_ip_fragment_offset = output_ip_fragment_offset_reg;
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assign output_ip_ttl = output_ip_ttl_reg;
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assign output_ip_protocol = output_ip_protocol_reg;
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assign output_ip_header_checksum = output_ip_header_checksum_reg;
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assign output_ip_source_ip = output_ip_source_ip_reg;
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assign output_ip_dest_ip = output_ip_dest_ip_reg;
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assign output_ip_payload_tdata = output_ip_payload_tdata_reg;
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assign output_ip_payload_tkeep = output_ip_payload_tkeep_reg;
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assign output_ip_payload_tvalid = output_ip_payload_tvalid_reg;
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assign output_ip_payload_tlast = output_ip_payload_tlast_reg;
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assign output_ip_payload_tuser = output_ip_payload_tuser_reg;
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assign busy = busy_reg;
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assign error_header_early_termination = error_header_early_termination_reg;
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assign error_payload_early_termination = error_payload_early_termination_reg;
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assign error_invalid_header = error_invalid_header_reg;
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assign error_invalid_checksum = error_invalid_checksum_reg;
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function [3:0] keep2count;
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input [7:0] k;
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case (k)
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8'b00000000: keep2count = 0;
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8'b00000001: keep2count = 1;
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8'b00000011: keep2count = 2;
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8'b00000111: keep2count = 3;
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8'b00001111: keep2count = 4;
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8'b00011111: keep2count = 5;
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8'b00111111: keep2count = 6;
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8'b01111111: keep2count = 7;
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8'b11111111: keep2count = 8;
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endcase
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endfunction
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function [7:0] count2keep;
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input [3:0] k;
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case (k)
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4'd0: count2keep = 8'b00000000;
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4'd1: count2keep = 8'b00000001;
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4'd2: count2keep = 8'b00000011;
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4'd3: count2keep = 8'b00000111;
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4'd4: count2keep = 8'b00001111;
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4'd5: count2keep = 8'b00011111;
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4'd6: count2keep = 8'b00111111;
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4'd7: count2keep = 8'b01111111;
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4'd8: count2keep = 8'b11111111;
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endcase
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endfunction
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always @* begin
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shift_eth_payload_tdata[31:0] = save_eth_payload_tdata_reg[63:32];
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shift_eth_payload_tkeep[3:0] = save_eth_payload_tkeep_reg[7:4];
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shift_eth_payload_extra_cycle = save_eth_payload_tlast_reg & (save_eth_payload_tkeep_reg[7:4] != 0);
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if (shift_eth_payload_extra_cycle) begin
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shift_eth_payload_tdata[63:32] = 0;
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shift_eth_payload_tkeep[7:4] = 0;
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shift_eth_payload_tvalid = 1;
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shift_eth_payload_tlast = save_eth_payload_tlast_reg;
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shift_eth_payload_tuser = save_eth_payload_tuser_reg;
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shift_eth_payload_input_tready = flush_save;
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end else begin
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shift_eth_payload_tdata[63:32] = input_eth_payload_tdata[31:0];
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shift_eth_payload_tkeep[7:4] = input_eth_payload_tkeep[3:0];
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shift_eth_payload_tvalid = input_eth_payload_tvalid;
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shift_eth_payload_tlast = (input_eth_payload_tlast & (input_eth_payload_tkeep[7:4] == 0));
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shift_eth_payload_tuser = (input_eth_payload_tuser & (input_eth_payload_tkeep[7:4] == 0));
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shift_eth_payload_input_tready = ~(input_eth_payload_tlast & input_eth_payload_tvalid & transfer_in_save);
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end
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end
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always @* begin
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state_next = 2'bz;
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flush_save = 0;
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transfer_in_save = 0;
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transfer_save_out = 0;
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transfer_in_out = 0;
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transfer_in_temp = 0;
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transfer_temp_out = 0;
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assert_tlast = 0;
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assert_tuser = 0;
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tkeep_mask = 8'hff;
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store_eth_hdr = 0;
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store_hdr_word_0 = 0;
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store_hdr_word_1 = 0;
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store_hdr_word_2 = 0;
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frame_ptr_next = frame_ptr_reg;
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hdr_sum_temp = 0;
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hdr_sum_next = hdr_sum_reg;
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hdr_sum_temp_a_next = hdr_sum_temp_a_reg;
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hdr_sum_temp_b_next = hdr_sum_temp_b_reg;
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output_ip_hdr_valid_next = output_ip_hdr_valid_reg & ~output_ip_hdr_ready;
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error_header_early_termination_next = 0;
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error_payload_early_termination_next = 0;
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error_invalid_header_next = 0;
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error_invalid_checksum_next = 0;
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case (state_reg)
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STATE_IDLE: begin
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// idle state - wait for header
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frame_ptr_next = 0;
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hdr_sum_next = 0;
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flush_save = 1;
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if (input_eth_hdr_ready & input_eth_hdr_valid) begin
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frame_ptr_next = 0;
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store_eth_hdr = 1;
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state_next = STATE_READ_HEADER;
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_READ_HEADER: begin
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// read header state
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if (input_eth_payload_tvalid) begin
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// word transfer in - store it
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frame_ptr_next = frame_ptr_reg+8;
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transfer_in_save = 1;
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state_next = STATE_READ_HEADER;
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case (frame_ptr_reg)
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8'h00: begin
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store_hdr_word_0 = 1;
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hdr_sum_temp = input_eth_payload_tdata[15:0] +
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input_eth_payload_tdata[31:16] +
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input_eth_payload_tdata[47:32] +
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input_eth_payload_tdata[63:48];
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hdr_sum_temp = hdr_sum_temp[15:0] + hdr_sum_temp[31:16];
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hdr_sum_temp_a_next = hdr_sum_temp[15:0] + hdr_sum_temp[16];
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end
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8'h08: begin
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store_hdr_word_1 = 1;
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hdr_sum_temp = input_eth_payload_tdata[15:0] +
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input_eth_payload_tdata[31:16] +
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input_eth_payload_tdata[47:32] +
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input_eth_payload_tdata[63:48];
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hdr_sum_temp = hdr_sum_temp[15:0] + hdr_sum_temp[31:16];
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hdr_sum_temp_b_next = hdr_sum_temp[15:0] + hdr_sum_temp[16];
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end
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8'h10: begin
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store_hdr_word_2 = 1;
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hdr_sum_temp = input_eth_payload_tdata[15:0] +
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input_eth_payload_tdata[31:16] +
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hdr_sum_temp_a_reg +
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hdr_sum_temp_b_reg;
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hdr_sum_temp = hdr_sum_temp[15:0] + hdr_sum_temp[31:16];
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hdr_sum_next = hdr_sum_temp[15:0] + hdr_sum_temp[16];
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frame_ptr_next = frame_ptr_reg+4;
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if (output_ip_version_reg != 4 || output_ip_ihl_reg != 5) begin
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error_invalid_header_next = 1;
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state_next = STATE_WAIT_LAST;
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end else if (hdr_sum_next != 16'hffff) begin
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error_invalid_checksum_next = 1;
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state_next = STATE_WAIT_LAST;
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end else begin
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output_ip_hdr_valid_next = 1;
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state_next = STATE_READ_PAYLOAD_IDLE;
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end
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end
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endcase
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if (shift_eth_payload_tlast) begin
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state_next = STATE_IDLE;
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output_ip_hdr_valid_next = 0;
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error_header_early_termination_next = 1;
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error_invalid_header_next = 0;
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error_invalid_checksum_next = 0;
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end
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end else begin
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state_next = STATE_READ_HEADER;
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end
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end
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STATE_READ_PAYLOAD_IDLE: begin
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// idle; no data in registers
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if (shift_eth_payload_tvalid) begin
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// word transfer in - store it in output register
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transfer_in_save = 1;
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transfer_in_out = 1;
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frame_ptr_next = frame_ptr_reg+keep2count(shift_eth_payload_tkeep);
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if (frame_ptr_next >= output_ip_length_reg) begin
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// have entire payload
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frame_ptr_next = output_ip_length_reg;
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tkeep_mask = count2keep(output_ip_length_reg - frame_ptr_reg);
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if (shift_eth_payload_tlast) begin
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state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
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end else begin
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state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST;
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end
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end else begin
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if (shift_eth_payload_tlast) begin
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// end of frame, but length does not match
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assert_tuser = 1;
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assert_tlast = 1;
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error_payload_early_termination_next = 1;
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state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
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end else begin
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state_next = STATE_READ_PAYLOAD_TRANSFER;
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end
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end
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end else begin
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state_next = STATE_READ_PAYLOAD_IDLE;
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end
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end
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STATE_READ_PAYLOAD_TRANSFER: begin
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// read payload; data in output register
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if (shift_eth_payload_tvalid & output_ip_payload_tready) begin
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// word transfer through - update output register
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transfer_in_save = 1;
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transfer_in_out = 1;
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frame_ptr_next = frame_ptr_reg+keep2count(shift_eth_payload_tkeep);
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if (frame_ptr_next >= output_ip_length_reg) begin
|
|
// have entire payload
|
|
frame_ptr_next = output_ip_length_reg;
|
|
tkeep_mask = count2keep(output_ip_length_reg - frame_ptr_reg);
|
|
if (shift_eth_payload_tlast) begin
|
|
state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
|
|
end else begin
|
|
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST;
|
|
end
|
|
end else begin
|
|
if (shift_eth_payload_tlast) begin
|
|
// end of frame, but length does not match
|
|
assert_tuser = 1;
|
|
assert_tlast = 1;
|
|
error_payload_early_termination_next = 1;
|
|
state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
|
|
end else begin
|
|
state_next = STATE_READ_PAYLOAD_TRANSFER;
|
|
end
|
|
end
|
|
end else if (~shift_eth_payload_tvalid & output_ip_payload_tready) begin
|
|
// word transfer out - go back to idle
|
|
state_next = STATE_READ_PAYLOAD_IDLE;
|
|
end else if (shift_eth_payload_tvalid & ~output_ip_payload_tready) begin
|
|
// word transfer in - store in temp
|
|
transfer_in_save = 1;
|
|
transfer_in_temp = 1;
|
|
frame_ptr_next = frame_ptr_reg+keep2count(shift_eth_payload_tkeep);
|
|
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT;
|
|
if (frame_ptr_next >= output_ip_length_reg) begin
|
|
// have entire payload
|
|
frame_ptr_next = output_ip_length_reg;
|
|
tkeep_mask = count2keep(output_ip_length_reg - frame_ptr_reg);
|
|
if (~shift_eth_payload_tlast) begin
|
|
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST_WAIT;
|
|
end
|
|
end
|
|
end else begin
|
|
state_next = STATE_READ_PAYLOAD_TRANSFER;
|
|
end
|
|
end
|
|
STATE_READ_PAYLOAD_TRANSFER_WAIT: begin
|
|
// read payload; data in both output and temp registers
|
|
if (output_ip_payload_tready) begin
|
|
// transfer out - move temp to output
|
|
transfer_temp_out = 1;
|
|
if (temp_ip_payload_tlast_reg) begin
|
|
if (frame_ptr_next < output_ip_length_reg) begin
|
|
// end of frame, but length does not match
|
|
assert_tuser = 1;
|
|
assert_tlast = 1;
|
|
error_payload_early_termination_next = 1;
|
|
end
|
|
state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
|
|
end else begin
|
|
if (frame_ptr_next >= output_ip_length_reg) begin
|
|
// not end of frame, but we have the entire payload
|
|
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST;
|
|
end else begin
|
|
state_next = STATE_READ_PAYLOAD_TRANSFER;
|
|
end
|
|
end
|
|
end else begin
|
|
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT;
|
|
end
|
|
end
|
|
STATE_READ_PAYLOAD_TRANSFER_LAST: begin
|
|
// read last payload word; data in output register; do not accept new data
|
|
if (output_ip_payload_tready) begin
|
|
// word transfer out - done
|
|
state_next = STATE_IDLE;
|
|
end else begin
|
|
state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
|
|
end
|
|
end
|
|
STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST: begin
|
|
// wait for end of frame; data in output register; read and discard
|
|
if (shift_eth_payload_tvalid) begin
|
|
transfer_in_save = 1;
|
|
if (shift_eth_payload_tlast) begin
|
|
// assert tlast and transfer tuser
|
|
assert_tlast = 1;
|
|
assert_tuser = shift_eth_payload_tuser;
|
|
state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
|
|
end else begin
|
|
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST;
|
|
end
|
|
end else begin
|
|
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST;
|
|
end
|
|
end
|
|
STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST_WAIT: begin
|
|
// wait for end of frame; data in both output and temp registers; read and discard
|
|
if (output_ip_payload_tready) begin
|
|
// transfer out - move temp to output
|
|
transfer_temp_out = 1;
|
|
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST;
|
|
end else begin
|
|
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST_WAIT;
|
|
end
|
|
end
|
|
STATE_WAIT_LAST: begin
|
|
// wait for end of frame; read and discard
|
|
if (shift_eth_payload_tvalid) begin
|
|
transfer_in_save = 1;
|
|
if (shift_eth_payload_tlast) begin
|
|
state_next = STATE_IDLE;
|
|
end else begin
|
|
state_next = STATE_WAIT_LAST;
|
|
end
|
|
end else begin
|
|
state_next = STATE_WAIT_LAST;
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always @(posedge clk or posedge rst) begin
|
|
if (rst) begin
|
|
state_reg <= STATE_IDLE;
|
|
frame_ptr_reg <= 0;
|
|
hdr_sum_reg <= 0;
|
|
hdr_sum_temp_a_reg <= 0;
|
|
hdr_sum_temp_b_reg <= 0;
|
|
input_eth_hdr_ready_reg <= 0;
|
|
input_eth_payload_tready_reg <= 0;
|
|
output_ip_hdr_valid_reg <= 0;
|
|
output_eth_dest_mac_reg <= 0;
|
|
output_eth_src_mac_reg <= 0;
|
|
output_eth_type_reg <= 0;
|
|
output_ip_version_reg <= 0;
|
|
output_ip_ihl_reg <= 0;
|
|
output_ip_dscp_reg <= 0;
|
|
output_ip_ecn_reg <= 0;
|
|
output_ip_length_reg <= 0;
|
|
output_ip_identification_reg <= 0;
|
|
output_ip_flags_reg <= 0;
|
|
output_ip_fragment_offset_reg <= 0;
|
|
output_ip_ttl_reg <= 0;
|
|
output_ip_protocol_reg <= 0;
|
|
output_ip_header_checksum_reg <= 0;
|
|
output_ip_source_ip_reg <= 0;
|
|
output_ip_dest_ip_reg <= 0;
|
|
output_ip_payload_tdata_reg <= 0;
|
|
output_ip_payload_tvalid_reg <= 0;
|
|
output_ip_payload_tlast_reg <= 0;
|
|
output_ip_payload_tuser_reg <= 0;
|
|
temp_ip_payload_tdata_reg <= 0;
|
|
temp_ip_payload_tlast_reg <= 0;
|
|
temp_ip_payload_tuser_reg <= 0;
|
|
busy_reg <= 0;
|
|
error_header_early_termination_reg <= 0;
|
|
error_payload_early_termination_reg <= 0;
|
|
error_invalid_header_reg <= 0;
|
|
error_invalid_checksum_reg <= 0;
|
|
end else begin
|
|
state_reg <= state_next;
|
|
|
|
frame_ptr_reg <= frame_ptr_next;
|
|
|
|
hdr_sum_reg <= hdr_sum_next;
|
|
hdr_sum_temp_a_reg <= hdr_sum_temp_a_next;
|
|
hdr_sum_temp_b_reg <= hdr_sum_temp_b_next;
|
|
|
|
output_ip_hdr_valid_reg <= output_ip_hdr_valid_next;
|
|
|
|
error_header_early_termination_reg <= error_header_early_termination_next;
|
|
error_payload_early_termination_reg <= error_payload_early_termination_next;
|
|
error_invalid_header_reg <= error_invalid_header_next;
|
|
error_invalid_checksum_reg <= error_invalid_checksum_next;
|
|
|
|
busy_reg <= state_next != STATE_IDLE;
|
|
|
|
// generate valid outputs
|
|
case (state_next)
|
|
STATE_IDLE: begin
|
|
// idle; accept new data
|
|
input_eth_hdr_ready_reg <= ~output_ip_hdr_valid;
|
|
input_eth_payload_tready_reg <= 0;
|
|
output_ip_payload_tvalid_reg <= 0;
|
|
end
|
|
STATE_READ_HEADER: begin
|
|
// read header; accept new data
|
|
input_eth_hdr_ready_reg <= 0;
|
|
input_eth_payload_tready_reg <= shift_eth_payload_input_tready;
|
|
output_ip_payload_tvalid_reg <= 0;
|
|
end
|
|
STATE_READ_PAYLOAD_IDLE: begin
|
|
// read payload; no data in registers; accept new data
|
|
input_eth_hdr_ready_reg <= 0;
|
|
input_eth_payload_tready_reg <= shift_eth_payload_input_tready;
|
|
output_ip_payload_tvalid_reg <= 0;
|
|
end
|
|
STATE_READ_PAYLOAD_TRANSFER: begin
|
|
// read payload; data in output register; accept new data
|
|
input_eth_hdr_ready_reg <= 0;
|
|
input_eth_payload_tready_reg <= shift_eth_payload_input_tready;
|
|
output_ip_payload_tvalid_reg <= 1;
|
|
end
|
|
STATE_READ_PAYLOAD_TRANSFER_WAIT: begin
|
|
// read payload; data in output and temp registers; do not accept new data
|
|
input_eth_hdr_ready_reg <= 0;
|
|
input_eth_payload_tready_reg <= 0;
|
|
output_ip_payload_tvalid_reg <= 1;
|
|
end
|
|
STATE_READ_PAYLOAD_TRANSFER_LAST: begin
|
|
// read last payload word; data in output register; do not accept new data
|
|
input_eth_hdr_ready_reg <= 0;
|
|
input_eth_payload_tready_reg <= 0;
|
|
output_ip_payload_tvalid_reg <= 1;
|
|
end
|
|
STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST: begin
|
|
// wait for end of frame; data in output register; read and discard
|
|
input_eth_hdr_ready_reg <= 0;
|
|
input_eth_payload_tready_reg <= shift_eth_payload_input_tready;
|
|
output_ip_payload_tvalid_reg <= 0;
|
|
end
|
|
STATE_READ_PAYLOAD_TRANSFER_WAIT_LAST_WAIT: begin
|
|
// wait for end of frame; data in output and temp registers; do not accept new data
|
|
input_eth_hdr_ready_reg <= 0;
|
|
input_eth_payload_tready_reg <= 0;
|
|
output_ip_payload_tvalid_reg <= 1;
|
|
end
|
|
STATE_WAIT_LAST: begin
|
|
// wait for end of frame; read and discard
|
|
input_eth_hdr_ready_reg <= 0;
|
|
input_eth_payload_tready_reg <= shift_eth_payload_input_tready;
|
|
output_ip_payload_tvalid_reg <= 0;
|
|
end
|
|
endcase
|
|
|
|
// datapath
|
|
if (store_eth_hdr) begin
|
|
output_eth_dest_mac_reg <= input_eth_dest_mac;
|
|
output_eth_src_mac_reg <= input_eth_src_mac;
|
|
output_eth_type_reg <= input_eth_type;
|
|
end
|
|
|
|
if (store_hdr_word_0) begin
|
|
{output_ip_version_reg, output_ip_ihl_reg} <= input_eth_payload_tdata[ 7: 0];
|
|
{output_ip_dscp_reg, output_ip_ecn_reg} <= input_eth_payload_tdata[15: 8];
|
|
output_ip_length_reg[15: 8] <= input_eth_payload_tdata[23:16];
|
|
output_ip_length_reg[ 7: 0] <= input_eth_payload_tdata[31:24];
|
|
output_ip_identification_reg[15: 8] <= input_eth_payload_tdata[39:32];
|
|
output_ip_identification_reg[ 7: 0] <= input_eth_payload_tdata[47:40];
|
|
{output_ip_flags_reg, output_ip_fragment_offset_reg[12:8]} <= input_eth_payload_tdata[55:48];
|
|
output_ip_fragment_offset_reg[ 7:0] <= input_eth_payload_tdata[63:56];
|
|
end
|
|
|
|
if (store_hdr_word_1) begin
|
|
output_ip_ttl_reg <= input_eth_payload_tdata[ 7: 0];
|
|
output_ip_protocol_reg <= input_eth_payload_tdata[15: 8];
|
|
output_ip_header_checksum_reg[15: 8] <= input_eth_payload_tdata[23:16];
|
|
output_ip_header_checksum_reg[ 7: 0] <= input_eth_payload_tdata[31:24];
|
|
output_ip_source_ip_reg[31:24] <= input_eth_payload_tdata[39:32];
|
|
output_ip_source_ip_reg[23:16] <= input_eth_payload_tdata[47:40];
|
|
output_ip_source_ip_reg[15: 8] <= input_eth_payload_tdata[55:48];
|
|
output_ip_source_ip_reg[ 7: 0] <= input_eth_payload_tdata[63:56];
|
|
end
|
|
|
|
if (store_hdr_word_2) begin
|
|
output_ip_dest_ip_reg[31:24] <= input_eth_payload_tdata[ 7: 0];
|
|
output_ip_dest_ip_reg[23:16] <= input_eth_payload_tdata[15: 8];
|
|
output_ip_dest_ip_reg[15: 8] <= input_eth_payload_tdata[23:16];
|
|
output_ip_dest_ip_reg[ 7: 0] <= input_eth_payload_tdata[31:24];
|
|
end
|
|
|
|
if (transfer_in_out) begin
|
|
output_ip_payload_tdata_reg <= shift_eth_payload_tdata;
|
|
output_ip_payload_tkeep_reg <= shift_eth_payload_tkeep & tkeep_mask;
|
|
output_ip_payload_tlast_reg <= shift_eth_payload_tlast;
|
|
output_ip_payload_tuser_reg <= shift_eth_payload_tuser;
|
|
end else if (transfer_in_temp) begin
|
|
temp_ip_payload_tdata_reg <= shift_eth_payload_tdata;
|
|
temp_ip_payload_tkeep_reg <= shift_eth_payload_tkeep & tkeep_mask;
|
|
temp_ip_payload_tlast_reg <= shift_eth_payload_tlast;
|
|
temp_ip_payload_tuser_reg <= shift_eth_payload_tuser;
|
|
end else if (transfer_temp_out) begin
|
|
output_ip_payload_tdata_reg <= temp_ip_payload_tdata_reg;
|
|
output_ip_payload_tkeep_reg <= temp_ip_payload_tkeep_reg;
|
|
output_ip_payload_tlast_reg <= temp_ip_payload_tlast_reg;
|
|
output_ip_payload_tuser_reg <= temp_ip_payload_tuser_reg;
|
|
end
|
|
|
|
if (flush_save) begin
|
|
save_eth_payload_tdata_reg <= 0;
|
|
save_eth_payload_tkeep_reg <= 0;
|
|
save_eth_payload_tlast_reg <= 0;
|
|
save_eth_payload_tuser_reg <= 0;
|
|
end else if (transfer_in_save & ~shift_eth_payload_extra_cycle) begin
|
|
save_eth_payload_tdata_reg <= input_eth_payload_tdata;
|
|
save_eth_payload_tkeep_reg <= input_eth_payload_tkeep;
|
|
save_eth_payload_tlast_reg <= input_eth_payload_tlast;
|
|
save_eth_payload_tuser_reg <= input_eth_payload_tuser;
|
|
end
|
|
|
|
if (assert_tlast) output_ip_payload_tlast_reg <= 1;
|
|
if (assert_tuser) output_ip_payload_tuser_reg <= 1;
|
|
end
|
|
end
|
|
|
|
endmodule
|