FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-02-04 07:13:13 +08:00
Code Issues Projects Releases Wiki Activity
verilog-ethernet/example/HTG640/fpga/common
History
Alex Forencich b1177eb4ed Rename HXT100G to HTG-640 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-07-21 18:17:26 -07:00
..
xilinx.mk
Rename HXT100G to HTG-640
2023-07-21 18:17:26 -07:00