FPGA/verilog-ethernet
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verilog-ethernet/rtl
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Alex Forencich 2199a15c75 Force possible floating point parameter value to integer when taking clog2 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-11-01 23:56:27 -07:00
..
arp_cache.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
arp_eth_rx.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
arp_eth_tx.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
arp.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
axis_baser_rx_64.v
Rework MAC PTP timestamp adjustment logic
2022-07-25 16:35:26 -07:00
axis_baser_tx_64.v
Rework MAC PTP timestamp adjustment logic
2022-07-25 16:35:26 -07:00
axis_eth_fcs_check_64.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
axis_eth_fcs_check.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
axis_eth_fcs_insert_64.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
axis_eth_fcs_insert.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
axis_eth_fcs.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
axis_gmii_rx.v
Remove unnecessary resets
2022-07-24 10:14:54 -07:00
axis_gmii_tx.v
Rework MAC frame padding logic
2022-07-24 22:46:03 -07:00
axis_xgmii_rx_32.v
Use generate blocks for Ethernet FCS computation
2022-07-24 19:52:55 -07:00
axis_xgmii_rx_64.v
Rework MAC PTP timestamp adjustment logic
2022-07-25 16:35:26 -07:00
axis_xgmii_tx_32.v
Remove unnecessary CRC resets
2022-07-25 15:03:03 -07:00
axis_xgmii_tx_64.v
Rework MAC PTP timestamp adjustment logic
2022-07-25 16:35:26 -07:00
eth_arb_mux.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
eth_axis_rx.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
eth_axis_tx.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
eth_demux.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
eth_mac_1g_fifo.v
Update FIFO PIPELINE_OUTPUT to RAM_PIPELINE
2022-11-01 23:56:11 -07:00
eth_mac_1g_gmii_fifo.v
Update FIFO PIPELINE_OUTPUT to RAM_PIPELINE
2022-11-01 23:56:11 -07:00
eth_mac_1g_gmii.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
eth_mac_1g_rgmii_fifo.v
Update FIFO PIPELINE_OUTPUT to RAM_PIPELINE
2022-11-01 23:56:11 -07:00
eth_mac_1g_rgmii.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
eth_mac_1g.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
eth_mac_10g_fifo.v
Update FIFO PIPELINE_OUTPUT to RAM_PIPELINE
2022-11-01 23:56:11 -07:00
eth_mac_10g.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
eth_mac_mii_fifo.v
Update FIFO PIPELINE_OUTPUT to RAM_PIPELINE
2022-11-01 23:56:11 -07:00
eth_mac_mii.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
eth_mac_phy_10g_fifo.v
Update FIFO PIPELINE_OUTPUT to RAM_PIPELINE
2022-11-01 23:56:11 -07:00
eth_mac_phy_10g_rx.v
Add PHY RX status output for a more reliable link up indication
2022-05-16 23:22:30 -07:00
eth_mac_phy_10g_tx.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
eth_mac_phy_10g.v
Add PHY RX status output for a more reliable link up indication
2022-05-16 23:22:30 -07:00
eth_mux.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
eth_phy_10g_rx_ber_mon.v
Force possible floating point parameter value to integer when taking clog2
2022-11-01 23:56:27 -07:00
eth_phy_10g_rx_frame_sync.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
eth_phy_10g_rx_if.v
Add PHY RX status output for a more reliable link up indication
2022-05-16 23:22:30 -07:00
eth_phy_10g_rx_watchdog.v
Force possible floating point parameter value to integer when taking clog2
2022-11-01 23:56:27 -07:00
eth_phy_10g_rx.v
Add PHY RX status output for a more reliable link up indication
2022-05-16 23:22:30 -07:00
eth_phy_10g_tx_if.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
eth_phy_10g_tx.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
eth_phy_10g.v
Add PHY RX status output for a more reliable link up indication
2022-05-16 23:22:30 -07:00
gmii_phy_if.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
iddr.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ip_64.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ip_arb_mux.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
ip_complete_64.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ip_complete.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ip_demux.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
ip_eth_rx_64.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
ip_eth_rx.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
ip_eth_tx_64.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
ip_eth_tx.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
ip_mux.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
ip.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
lfsr.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
mii_phy_if.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
oddr.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ptp_clock_cdc.v
Timing optimization of PTP modules
2022-07-22 22:57:44 -07:00
ptp_clock.v
Fix assignment type
2022-10-20 09:21:34 -07:00
ptp_perout.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ptp_tag_insert.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ptp_ts_extract.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
rgmii_phy_if.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ssio_ddr_in_diff.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ssio_ddr_in.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ssio_ddr_out_diff.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ssio_ddr_out.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ssio_sdr_in_diff.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ssio_sdr_in.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ssio_sdr_out_diff.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ssio_sdr_out.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
udp_64.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
udp_arb_mux.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
udp_checksum_gen_64.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
udp_checksum_gen.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
udp_complete_64.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
udp_complete.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
udp_demux.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
udp_ip_rx_64.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
udp_ip_rx.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
udp_ip_tx_64.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
udp_ip_tx.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
udp_mux.v
Rewrite early ready condition
2022-05-15 17:47:30 -07:00
udp.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
xgmii_baser_dec_64.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
xgmii_baser_enc_64.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
xgmii_deinterleave.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
xgmii_interleave.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00