FPGA/verilog-ethernet
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verilog-ethernet/example/DE2-115/fpga/rtl
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Alex Forencich 3898cf21ed Add DE2-115 example design
2020-07-10 15:38:43 -07:00
..
debounce_switch.v
Add DE2-115 example design
2020-07-10 15:38:43 -07:00
fpga_core.v
Add DE2-115 example design
2020-07-10 15:38:43 -07:00
fpga.v
Add DE2-115 example design
2020-07-10 15:38:43 -07:00
hex_display.v
Add DE2-115 example design
2020-07-10 15:38:43 -07:00
sync_signal.v
Add DE2-115 example design
2020-07-10 15:38:43 -07:00