verilog-ethernet/axis_xgmii_tx_64 at 22b3bacf516adf4395003314b8eeab790c779537 - verilog-ethernet - Gitea: Git with a cup of tea

FPGA/verilog-ethernet

mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00

History

Alex Forencich 22b3bacf51 Update attribute name

2021-03-05 23:03:41 -08:00

..

Makefile

Rework sim_build output directory, fix default makefile target

2020-12-29 14:47:12 -08:00

test_axis_xgmii_tx_64.py

Update attribute name

2021-03-05 23:03:41 -08:00