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FPGA
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verilog-ethernet
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verilog-ethernet
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example
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ATLYS
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fpga
History
Alex Forencich
b38c643384
Add more implementation parameters to gmii_phy_if
2016-06-28 19:35:52 -07:00
..
common
Add example design for Digilent Atlys board
2015-02-28 20:05:05 -08:00
fpga
Replace eth_crc modules for generic lfsr module
2016-06-28 17:31:58 -07:00
lib
Add example design for Digilent Atlys board
2015-02-28 20:05:05 -08:00
rtl
Add more implementation parameters to gmii_phy_if
2016-06-28 19:35:52 -07:00
tb
Replace eth_crc modules for generic lfsr module
2016-06-28 17:31:58 -07:00
clock.ucf
Add example design for Digilent Atlys board
2015-02-28 20:05:05 -08:00
fpga.ucf
Add example design for Digilent Atlys board
2015-02-28 20:05:05 -08:00
Makefile
Update example design
2016-01-08 01:32:04 -08:00
