mirror of
https://github.com/alexforencich/verilog-ethernet.git
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552 lines
21 KiB
Verilog
552 lines
21 KiB
Verilog
/*
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Copyright (c) 2014 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* IP ethernet frame transmitter (IP frame in, Ethernet frame out)
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*/
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module ip_eth_tx
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(
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input wire clk,
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input wire rst,
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/*
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* IP frame input
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*/
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input wire input_ip_hdr_valid,
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output wire input_ip_hdr_ready,
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input wire [47:0] input_eth_dest_mac,
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input wire [47:0] input_eth_src_mac,
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input wire [15:0] input_eth_type,
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input wire [5:0] input_ip_dscp,
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input wire [1:0] input_ip_ecn,
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input wire [15:0] input_ip_length,
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input wire [15:0] input_ip_identification,
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input wire [2:0] input_ip_flags,
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input wire [12:0] input_ip_fragment_offset,
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input wire [7:0] input_ip_ttl,
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input wire [7:0] input_ip_protocol,
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input wire [31:0] input_ip_source_ip,
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input wire [31:0] input_ip_dest_ip,
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input wire [7:0] input_ip_payload_tdata,
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input wire input_ip_payload_tvalid,
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output wire input_ip_payload_tready,
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input wire input_ip_payload_tlast,
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input wire input_ip_payload_tuser,
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/*
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* Ethernet frame output
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*/
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output wire output_eth_hdr_valid,
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input wire output_eth_hdr_ready,
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output wire [47:0] output_eth_dest_mac,
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output wire [47:0] output_eth_src_mac,
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output wire [15:0] output_eth_type,
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output wire [7:0] output_eth_payload_tdata,
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output wire output_eth_payload_tvalid,
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input wire output_eth_payload_tready,
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output wire output_eth_payload_tlast,
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output wire output_eth_payload_tuser,
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/*
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* Status signals
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*/
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output wire busy,
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output wire error_payload_early_termination
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);
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/*
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IP Frame
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Field Length
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Destination MAC address 6 octets
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Source MAC address 6 octets
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Ethertype (0x0800) 2 octets
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Version (4) 4 bits
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IHL (5-15) 4 bits
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DSCP (0) 6 bits
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ECN (0) 2 bits
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length 2 octets
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identification (0?) 2 octets
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flags (010) 3 bits
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fragment offset (0) 13 bits
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time to live (64?) 1 octet
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protocol 1 octet
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header checksum 2 octets
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source IP 4 octets
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destination IP 4 octets
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options (IHL-5)*4 octets
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payload length octets
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This module receives an Ethernet frame with decoded fields and decodes
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the AXI packet format. If the Ethertype does not match, the packet is
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discarded.
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*/
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localparam [2:0]
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STATE_IDLE = 3'd0,
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STATE_WRITE_HEADER = 3'd1,
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STATE_WRITE_PAYLOAD_IDLE = 3'd2,
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STATE_WRITE_PAYLOAD_TRANSFER = 3'd3,
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STATE_WRITE_PAYLOAD_TRANSFER_WAIT = 3'd4,
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STATE_WRITE_PAYLOAD_TRANSFER_LAST = 3'd5,
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STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST = 3'd6,
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STATE_WAIT_LAST = 3'd7;
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reg [2:0] state_reg = STATE_IDLE, state_next;
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// datapath control signals
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reg store_ip_hdr;
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reg [7:0] write_hdr_data;
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reg write_hdr_out;
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reg transfer_in_out;
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reg transfer_in_temp;
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reg transfer_temp_out;
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reg assert_tlast;
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reg assert_tuser;
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reg [15:0] frame_ptr_reg = 0, frame_ptr_next;
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reg [15:0] hdr_sum_reg = 0, hdr_sum_next;
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reg [5:0] ip_dscp_reg = 0;
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reg [1:0] ip_ecn_reg = 0;
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reg [15:0] ip_length_reg = 0;
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reg [15:0] ip_identification_reg = 0;
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reg [2:0] ip_flags_reg = 0;
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reg [12:0] ip_fragment_offset_reg = 0;
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reg [7:0] ip_ttl_reg = 0;
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reg [7:0] ip_protocol_reg = 0;
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reg [31:0] ip_source_ip_reg = 0;
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reg [31:0] ip_dest_ip_reg = 0;
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reg input_ip_hdr_ready_reg = 0;
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reg input_ip_payload_tready_reg = 0;
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reg output_eth_hdr_valid_reg = 0, output_eth_hdr_valid_next;
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reg [47:0] output_eth_dest_mac_reg = 0;
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reg [47:0] output_eth_src_mac_reg = 0;
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reg [15:0] output_eth_type_reg = 0;
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reg [7:0] output_eth_payload_tdata_reg = 0;
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reg output_eth_payload_tvalid_reg = 0;
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reg output_eth_payload_tlast_reg = 0;
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reg output_eth_payload_tuser_reg = 0;
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reg busy_reg = 0;
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reg error_payload_early_termination_reg = 0, error_payload_early_termination_next;
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reg [7:0] temp_eth_payload_tdata_reg = 0;
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reg temp_eth_payload_tlast_reg = 0;
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reg temp_eth_payload_tuser_reg = 0;
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assign input_ip_hdr_ready = input_ip_hdr_ready_reg;
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assign input_ip_payload_tready = input_ip_payload_tready_reg;
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assign output_eth_hdr_valid = output_eth_hdr_valid_reg;
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assign output_eth_dest_mac = output_eth_dest_mac_reg;
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assign output_eth_src_mac = output_eth_src_mac_reg;
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assign output_eth_type = output_eth_type_reg;
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assign output_eth_payload_tdata = output_eth_payload_tdata_reg;
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assign output_eth_payload_tvalid = output_eth_payload_tvalid_reg;
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assign output_eth_payload_tlast = output_eth_payload_tlast_reg;
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assign output_eth_payload_tuser = output_eth_payload_tuser_reg;
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assign busy = busy_reg;
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assign error_payload_early_termination = error_payload_early_termination_reg;
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function [15:0] add1c16b;
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input [15:0] a, b;
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reg [16:0] t;
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begin
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t = a+b;
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add1c16b = t[15:0] + t[16];
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end
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endfunction
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always @* begin
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state_next = 2'bz;
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store_ip_hdr = 0;
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write_hdr_data = 0;
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write_hdr_out = 0;
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transfer_in_out = 0;
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transfer_in_temp = 0;
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transfer_temp_out = 0;
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assert_tlast = 0;
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assert_tuser = 0;
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frame_ptr_next = frame_ptr_reg;
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hdr_sum_next = hdr_sum_reg;
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output_eth_hdr_valid_next = output_eth_hdr_valid_reg & ~output_eth_hdr_ready;
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error_payload_early_termination_next = 0;
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case (state_reg)
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STATE_IDLE: begin
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// idle state - wait for data
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frame_ptr_next = 0;
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if (input_ip_hdr_valid & input_ip_hdr_ready) begin
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store_ip_hdr = 1;
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write_hdr_out = 1;
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write_hdr_data = {4'd4, 4'd5}; // ip_version, ip_ihl
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output_eth_hdr_valid_next = 1;
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frame_ptr_next = 1;
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state_next = STATE_WRITE_HEADER;
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_WRITE_HEADER: begin
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// write header state
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if (output_eth_payload_tready) begin
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// word transfer out
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frame_ptr_next = frame_ptr_reg+1;
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state_next = STATE_WRITE_HEADER;
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write_hdr_out = 1;
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case (frame_ptr_reg)
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8'h01: begin
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write_hdr_data = {ip_dscp_reg, ip_ecn_reg};
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hdr_sum_next = {4'd4, 4'd5, ip_dscp_reg, ip_ecn_reg};
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end
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8'h02: begin
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write_hdr_data = ip_length_reg[15: 8];
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hdr_sum_next = add1c16b(hdr_sum_reg, ip_length_reg);
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end
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8'h03: begin
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write_hdr_data = ip_length_reg[ 7: 0];
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hdr_sum_next = add1c16b(hdr_sum_reg, ip_identification_reg);
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end
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8'h04: begin
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write_hdr_data = ip_identification_reg[15: 8];
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hdr_sum_next = add1c16b(hdr_sum_reg, {ip_flags_reg, ip_fragment_offset_reg});
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end
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8'h05: begin
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write_hdr_data = ip_identification_reg[ 7: 0];
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hdr_sum_next = add1c16b(hdr_sum_reg, {ip_ttl_reg, ip_protocol_reg});
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end
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8'h06: begin
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write_hdr_data = {ip_flags_reg, ip_fragment_offset_reg[12:8]};
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hdr_sum_next = add1c16b(hdr_sum_reg, ip_source_ip_reg[31:16]);
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end
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8'h07: begin
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write_hdr_data = ip_fragment_offset_reg[ 7: 0];
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hdr_sum_next = add1c16b(hdr_sum_reg, ip_source_ip_reg[15:0]);
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end
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8'h08: begin
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write_hdr_data = ip_ttl_reg;
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hdr_sum_next = add1c16b(hdr_sum_reg, ip_dest_ip_reg[31:16]);
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end
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8'h09: begin
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write_hdr_data = ip_protocol_reg;
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hdr_sum_next = add1c16b(hdr_sum_reg, ip_dest_ip_reg[15:0]);
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end
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8'h0A: write_hdr_data = ~hdr_sum_reg[15: 8];
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8'h0B: write_hdr_data = ~hdr_sum_reg[ 7: 0];
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8'h0C: write_hdr_data = ip_source_ip_reg[31:24];
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8'h0D: write_hdr_data = ip_source_ip_reg[23:16];
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8'h0E: write_hdr_data = ip_source_ip_reg[15: 8];
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8'h0F: write_hdr_data = ip_source_ip_reg[ 7: 0];
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8'h10: write_hdr_data = ip_dest_ip_reg[31:24];
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8'h11: write_hdr_data = ip_dest_ip_reg[23:16];
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8'h12: write_hdr_data = ip_dest_ip_reg[15: 8];
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8'h13: begin
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write_hdr_data = ip_dest_ip_reg[ 7: 0];
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state_next = STATE_WRITE_PAYLOAD_TRANSFER;
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end
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endcase
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end else begin
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state_next = STATE_WRITE_HEADER;
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end
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end
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STATE_WRITE_PAYLOAD_IDLE: begin
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// idle; no data in registers
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if (input_ip_payload_tvalid) begin
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// word transfer in - store it in output register
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transfer_in_out = 1;
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frame_ptr_next = frame_ptr_reg+1;
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if (input_ip_payload_tlast) begin
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if (frame_ptr_next != ip_length_reg) begin
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// end of frame, but length does not match
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assert_tuser = 1;
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error_payload_early_termination_next = 1;
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end
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state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
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end else begin
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if (frame_ptr_next == ip_length_reg) begin
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// not end of frame, but we have the entire payload
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state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST;
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end else begin
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state_next = STATE_WRITE_PAYLOAD_TRANSFER;
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end
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end
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end else begin
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state_next = STATE_WRITE_PAYLOAD_IDLE;
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end
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end
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STATE_WRITE_PAYLOAD_TRANSFER: begin
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// write payload; data in output register
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if (input_ip_payload_tvalid & output_eth_payload_tready) begin
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// word transfer through - update output register
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transfer_in_out = 1;
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frame_ptr_next = frame_ptr_reg+1;
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if (input_ip_payload_tlast) begin
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if (frame_ptr_next != ip_length_reg) begin
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// end of frame, but length does not match
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assert_tuser = 1;
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error_payload_early_termination_next = 1;
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end
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state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
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end else begin
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if (frame_ptr_next == ip_length_reg) begin
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// not end of frame, but we have the entire payload
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state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST;
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end else begin
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state_next = STATE_WRITE_PAYLOAD_TRANSFER;
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end
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end
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end else if (~input_ip_payload_tvalid & output_eth_payload_tready) begin
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// word transfer out - go back to idle
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state_next = STATE_WRITE_PAYLOAD_IDLE;
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end else if (input_ip_payload_tvalid & ~output_eth_payload_tready) begin
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// word transfer in - store in temp
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transfer_in_temp = 1;
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frame_ptr_next = frame_ptr_reg+1;
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state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT;
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end else begin
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state_next = STATE_WRITE_PAYLOAD_TRANSFER;
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end
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end
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STATE_WRITE_PAYLOAD_TRANSFER_WAIT: begin
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// write payload; data in both output and temp registers
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if (output_eth_payload_tready) begin
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// transfer out - move temp to output
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transfer_temp_out = 1;
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if (temp_eth_payload_tlast_reg) begin
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if (frame_ptr_next != ip_length_reg) begin
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// end of frame, but length does not match
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assert_tuser = 1;
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error_payload_early_termination_next = 1;
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end
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state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
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end else begin
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if (frame_ptr_next == ip_length_reg) begin
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// not end of frame, but we have the entire payload
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state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST;
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end else begin
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state_next = STATE_WRITE_PAYLOAD_TRANSFER;
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end
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end
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end else begin
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state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT;
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end
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end
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STATE_WRITE_PAYLOAD_TRANSFER_LAST: begin
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// write last payload word; data in output register; do not accept new data
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if (output_eth_payload_tready) begin
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// word transfer out - done
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
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end
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end
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STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST: begin
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// wait for end of frame; data in output register; read and discard
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if (input_ip_payload_tvalid) begin
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if (input_ip_payload_tlast) begin
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// assert tlast and transfer tuser
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assert_tlast = 1;
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assert_tuser = input_ip_payload_tuser;
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state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
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end else begin
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state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST;
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end
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end else begin
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state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST;
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end
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end
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STATE_WAIT_LAST: begin
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// wait for end of frame; read and discard
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if (input_ip_payload_tvalid) begin
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if (input_ip_payload_tlast) begin
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_WAIT_LAST;
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end
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end else begin
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state_next = STATE_WAIT_LAST;
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end
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end
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endcase
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end
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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state_reg <= STATE_IDLE;
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frame_ptr_reg <= 0;
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hdr_sum_reg <= 0;
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input_ip_hdr_ready_reg <= 0;
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input_ip_payload_tready_reg <= 0;
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ip_dscp_reg <= 0;
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ip_ecn_reg <= 0;
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ip_length_reg <= 0;
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ip_identification_reg <= 0;
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ip_flags_reg <= 0;
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ip_fragment_offset_reg <= 0;
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ip_ttl_reg <= 0;
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ip_protocol_reg <= 0;
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ip_source_ip_reg <= 0;
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ip_dest_ip_reg <= 0;
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output_eth_hdr_valid_reg <= 0;
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output_eth_dest_mac_reg <= 0;
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output_eth_src_mac_reg <= 0;
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output_eth_type_reg <= 0;
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output_eth_payload_tdata_reg <= 0;
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output_eth_payload_tvalid_reg <= 0;
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output_eth_payload_tlast_reg <= 0;
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output_eth_payload_tuser_reg <= 0;
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temp_eth_payload_tdata_reg <= 0;
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temp_eth_payload_tlast_reg <= 0;
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temp_eth_payload_tuser_reg <= 0;
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busy_reg <= 0;
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error_payload_early_termination_reg <= 0;
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end else begin
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state_reg <= state_next;
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frame_ptr_reg <= frame_ptr_next;
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hdr_sum_reg <= hdr_sum_next;
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output_eth_hdr_valid_reg <= output_eth_hdr_valid_next;
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busy_reg <= state_next != STATE_IDLE;
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error_payload_early_termination_reg <= error_payload_early_termination_next;
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// generate valid outputs
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case (state_next)
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STATE_IDLE: begin
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// idle; accept new data
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input_ip_hdr_ready_reg <= 1;
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input_ip_payload_tready_reg <= 0;
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output_eth_payload_tvalid_reg <= 0;
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end
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STATE_WRITE_HEADER: begin
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// write header
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input_ip_hdr_ready_reg <= 0;
|
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input_ip_payload_tready_reg <= 0;
|
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output_eth_payload_tvalid_reg <= 1;
|
|
end
|
|
STATE_WRITE_PAYLOAD_IDLE: begin
|
|
// write payload; no data in registers; accept new data
|
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input_ip_hdr_ready_reg <= 0;
|
|
input_ip_payload_tready_reg <= 1;
|
|
output_eth_payload_tvalid_reg <= 0;
|
|
end
|
|
STATE_WRITE_PAYLOAD_TRANSFER: begin
|
|
// write payload; data in output register; accept new data
|
|
input_ip_hdr_ready_reg <= 0;
|
|
input_ip_payload_tready_reg <= 1;
|
|
output_eth_payload_tvalid_reg <= 1;
|
|
end
|
|
STATE_WRITE_PAYLOAD_TRANSFER_WAIT: begin
|
|
// write payload; data in output and temp registers; do not accept new data
|
|
input_ip_hdr_ready_reg <= 0;
|
|
input_ip_payload_tready_reg <= 0;
|
|
output_eth_payload_tvalid_reg <= 1;
|
|
end
|
|
STATE_WRITE_PAYLOAD_TRANSFER_LAST: begin
|
|
// write last payload word; data in output register; do not accept new data
|
|
input_ip_hdr_ready_reg <= 0;
|
|
input_ip_payload_tready_reg <= 0;
|
|
output_eth_payload_tvalid_reg <= 1;
|
|
end
|
|
STATE_WRITE_PAYLOAD_TRANSFER_WAIT_LAST: begin
|
|
// wait for end of frame; data in output register; read and discard
|
|
input_ip_hdr_ready_reg <= 0;
|
|
input_ip_payload_tready_reg <= 1;
|
|
output_eth_payload_tvalid_reg <= 0;
|
|
end
|
|
STATE_WAIT_LAST: begin
|
|
// wait for end of frame; read and discard
|
|
input_ip_hdr_ready_reg <= 0;
|
|
input_ip_payload_tready_reg <= 1;
|
|
output_eth_payload_tvalid_reg <= 0;
|
|
end
|
|
endcase
|
|
|
|
if (store_ip_hdr) begin
|
|
output_eth_dest_mac_reg <= input_eth_dest_mac;
|
|
output_eth_src_mac_reg <= input_eth_src_mac;
|
|
output_eth_type_reg <= input_eth_type;
|
|
ip_dscp_reg <= input_ip_dscp;
|
|
ip_ecn_reg <= input_ip_ecn;
|
|
ip_length_reg <= input_ip_length;
|
|
ip_identification_reg <= input_ip_identification;
|
|
ip_flags_reg <= input_ip_flags;
|
|
ip_fragment_offset_reg <= input_ip_fragment_offset;
|
|
ip_ttl_reg <= input_ip_ttl;
|
|
ip_protocol_reg <= input_ip_protocol;
|
|
ip_source_ip_reg <= input_ip_source_ip;
|
|
ip_dest_ip_reg <= input_ip_dest_ip;
|
|
end
|
|
|
|
if (write_hdr_out) begin
|
|
output_eth_payload_tdata_reg <= write_hdr_data;
|
|
output_eth_payload_tlast_reg <= 0;
|
|
output_eth_payload_tuser_reg <= 0;
|
|
end else if (transfer_in_out) begin
|
|
output_eth_payload_tdata_reg <= input_ip_payload_tdata;
|
|
output_eth_payload_tlast_reg <= input_ip_payload_tlast;
|
|
output_eth_payload_tuser_reg <= input_ip_payload_tuser;
|
|
end else if (transfer_in_temp) begin
|
|
temp_eth_payload_tdata_reg <= input_ip_payload_tdata;
|
|
temp_eth_payload_tlast_reg <= input_ip_payload_tlast;
|
|
temp_eth_payload_tuser_reg <= input_ip_payload_tuser;
|
|
end else if (transfer_temp_out) begin
|
|
output_eth_payload_tdata_reg <= temp_eth_payload_tdata_reg;
|
|
output_eth_payload_tlast_reg <= temp_eth_payload_tlast_reg;
|
|
output_eth_payload_tuser_reg <= temp_eth_payload_tuser_reg;
|
|
end
|
|
|
|
if (assert_tlast) output_eth_payload_tlast_reg <= 1;
|
|
if (assert_tuser) output_eth_payload_tuser_reg <= 1;
|
|
end
|
|
end
|
|
|
|
endmodule
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