FPGA/verilog-ethernet
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verilog-ethernet/example/ATLYS/fpga
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Alex Forencich 27ed447005 Use common sync_reset module files
2020-03-27 18:27:45 -07:00
..
common
Add example design for Digilent Atlys board
2015-02-28 20:05:05 -08:00
fpga
Use common sync_reset module files
2020-03-27 18:27:45 -07:00
lib
Add example design for Digilent Atlys board
2015-02-28 20:05:05 -08:00
rtl
Use common sync_reset module files
2020-03-27 18:27:45 -07:00
tb
Update example designs
2019-07-18 17:13:47 -07:00
clock.ucf
Update Atlys example design
2017-05-31 19:35:40 -07:00
fpga.ucf
Update Atlys example design
2017-05-31 19:35:40 -07:00
Makefile
Update example design
2016-01-08 01:32:04 -08:00