FPGA/verilog-ethernet
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verilog-ethernet/example/VCU118/fpga_25g/rtl
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Alex Forencich 27ed447005 Use common sync_reset module files
2020-03-27 18:27:45 -07:00
..
debounce_switch.v
Add VCU118 25G example design
2019-06-19 23:25:06 -07:00
fpga_core.v
Parametrize Ethernet frame parsing
2020-02-21 21:37:57 -08:00
fpga.v
Use common sync_reset module files
2020-03-27 18:27:45 -07:00
mdio_master.v
Add VCU118 25G example design
2019-06-19 23:25:06 -07:00
sync_signal.v
Add VCU118 25G example design
2019-06-19 23:25:06 -07:00